公开(公告)号：US20210132823A1

公开(公告)日：2021-05-06

申请号：US17051961

申请日：2019-05-07

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Harish Reddy Singidi ,  Ting Luo ,  Kishore Kumar Miuchherla

IPC: G06F3/06

Abstract: Systems and methods are disclosed, including maintaining an error recovery data structure for a set of codewords (CWs) in a storage system and performing error recovery for the set of CWs using a set of error handing (EH) steps until each CW of the set of CWs are indicated as correctable in the error recovery data structure. The error recovery can include determining if each CW of the set of CWs is correctable by an EH step, storing indications of CWs determined correctable by the EH step in the error recovery data structure, determining if one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, and, in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, incrementing the specific EH step.

公开(公告)号：US10699780B2

公开(公告)日：2020-06-30

申请号：US16209152

申请日：2018-12-04

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean ,  Ting Luo

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10

Abstract: Devices and techniques to reduce corruption of received data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, in a first mode until the received data exceeds a threshold amount, and to transition from the first mode to a second mode after the received data exceeds the threshold amount.

公开(公告)号：US20200042201A1

公开(公告)日：2020-02-06

申请号：US16506372

申请日：2019-07-09

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Kulachet Tanpairoj ,  Harish Reddy Singidi ,  Ting Luo

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/1027

Abstract: Devices and techniques for managing partial superblocks in a NAND device are described herein. A set of superblock candidates is calculated. Here, a superblock may have a set of blocks that share a same position in each plane in each die of a NAND array of the NAND device. A set of partial super block candidates is also calculated. A partial superblock candidate is a superblock candidate that has at least one plane that has a bad block. A partial superblock use classification may then be obtained. Superblocks may be established for the NAND device by using members of the set of superblock candidates after removing the set of partial superblock candidates from the set of superblock candidates. Partial superblocks may then be established for classes of data in the NAND device according to the partial superblock use classification.

公开(公告)号：US20200005884A1

公开(公告)日：2020-01-02

申请号：US16410764

申请日：2019-05-13

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Scott Anthony Stoller ,  Preston Allen Thomson ,  Devin Batutis ,  Harish Reddy Singidi ,  Kulachet Tanpairoj

IPC: G11C29/38 ,  G11C29/44 ,  G06F11/07

Abstract: Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one or more cells that did not finish programming. The memory device may detect these cells and erase them or mark them for erasure.

公开(公告)号：US10522229B2

公开(公告)日：2019-12-31

申请号：US15691584

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Kulachet Tanpairoj ,  Harish Singidi ,  Jianmin Huang ,  Preston Thomson ,  Sebastien Andre Jean

IPC: G11C11/34 ,  G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56 ,  G11C16/34 ,  H01L27/11582 ,  H01L27/11556

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

公开(公告)号：US20190295660A1

公开(公告)日：2019-09-26

申请号：US16436567

申请日：2019-06-10

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi ,  Peter Sean Feeley ,  Sampath Ratnam ,  Kulachet Tanpairoj ,  Ting Luo

IPC: G11C16/26 ,  G11C16/34 ,  G11C29/02 ,  G11C16/04 ,  G11C16/28

Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.

公开(公告)号：US20240264771A1

公开(公告)日：2024-08-08

申请号：US18441911

申请日：2024-02-14

Applicant: Micron Technology, Inc.

Inventor： Tao Liu ,  Zhengang Chen ,  Ting Luo

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0679 ,  G11C16/10 ,  G11C16/26 ,  G06F2212/7206 ,  G11C16/0483

Abstract: Methods, systems, and devices for a corrective read of a memory device with reduced latency are described. A memory system may identify a read error based on accessing a memory device, and may select a trim setting for a performing a corrective read operation based on a data retention condition associated with the accessed memory device. Such a data retention condition may be associated with a data retention duration, or a cross-temperature condition, among other criteria or combinations thereof. In some implementations, the memory system may select from a subset of possible trim settings, which may be associated with relevant process corners. For example, the memory system may select between a first trim setting that is associated with a relatively large cross-temperature and a relatively short data retention duration and a second trim setting that is associated with a relatively small cross-temperature and a relatively long data retention duration.

公开(公告)号：US20240185926A1

公开(公告)日：2024-06-06

申请号：US18517903

申请日：2023-11-22

Applicant: Micron Technology, Inc.

Inventor： Huai-Yuan Tseng ,  Kishore Kumar Mucherla ,  William Charles Filipiak ,  Eric N. Lee ,  Andrew Bicksler ,  Ugo Russo ,  Niccolo' Righetti ,  Christian Caillat ,  Akira Goda ,  Ting Luo ,  Antonino Pollio

IPC: G11C16/10 ,  G11C16/16 ,  G11C16/34

CPC classification number: G11C16/102 ,  G11C16/16 ,  G11C16/3404

Abstract: A variety of applications can include one or more memory devices having user data preloaded for the application prior to reflowing the memory devices on the system platform of the application. A touch-up data refresh method can be implemented to gain read window budget and to improve retention slope to protect the preload content to tolerate reflow to the system platform. Techniques for data preload can include programming preload data into targeted blocks until the targeted blocks are programmed with the preload data and re-programming the preload data over the programmed preload data in the targeted blocks in a same set of memory cells, without an erase between programming and re-programming the preload data. Variations of such techniques can be used to prepare a memory device with preload data followed by performing a reflow of the memory device to a structure for an application to which the memory device is implemented.

公开(公告)号：US11907580B2

公开(公告)日：2024-02-20

申请号：US17645683

申请日：2021-12-22

Applicant: Micron Technology, Inc.

Inventor： Tao Liu ,  Zhengang Chen ,  Ting Luo

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0679 ,  G11C16/10 ,  G11C16/26 ,  G06F2212/7206 ,  G11C16/0483

Abstract: Methods, systems, and devices for a corrective read of a memory device with reduced latency are described. A memory system may identify a read error based on accessing a memory device, and may select a trim setting for a performing a corrective read operation based on a data retention condition associated with the accessed memory device. Such a data retention condition may be associated with a data retention duration, or a cross-temperature condition, among other criteria or combinations thereof. In some implementations, the memory system may select from a subset of possible trim settings, which may be associated with relevant process corners. For example, the memory system may select between a first trim setting that is associated with a relatively large cross-temperature and a relatively short data retention duration and a second trim setting that is associated with a relatively small cross-temperature and a relatively long data retention duration.

公开(公告)号：US20240028248A1

公开(公告)日：2024-01-25

申请号：US17868085

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Christina Papagianni ,  Zhenming Zhou ,  Ting Luo

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/064 ,  G06F3/0604

Abstract: Methods, systems, and devices for cross-temperature mitigation in a memory system are described. A memory system may determine a first temperature of the memory system. Based on the first temperature satisfying a first threshold, the memory system may write a set of data to a first block of the memory system that is configured with a first rate for performing scan operations to determine error information for the first block. The memory system may then determine a second temperature of the memory system after writing the set of data to the first block. Based on the second temperature satisfying a second threshold, the memory system may transfer the set of data to a second block of the memory system that is configured with a second rate for performing scan operations to determine error information for the second block.