公开(公告)号：US10079063B2

公开(公告)日：2018-09-18

申请号：US15847531

申请日：2017-12-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G11C7/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  G11C16/32

Abstract: Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a memory. A plurality of global access lines may be associated with the memory array. The global access line may be charged to a ready-access voltage before any access command has been received by the memory. The global access line may be maintained at the ready-access voltage during memory access operations until the receipt of a post-access command. The post-access command may reset the global access line to an inactive voltage.

公开(公告)号：US10050049B2

公开(公告)日：2018-08-14

申请号：US15041277

申请日：2016-02-11

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/115 ,  H01L27/24 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/1157 ,  H01L27/11573

Abstract: Various apparatuses, including three-dimensional (3D) memory devices and systems including the same, are described herein. In one embodiment, a 3D memory device can include at least two sources; at least two memory arrays respectively formed over and coupled to the at least two sources; and a source conductor electrically respectively coupled to the at least two sources using source contacts adjacent one or more edges of the source. Each of the at least two memory arrays can include memory cells, control gates, and data lines. There is no data line between an edge of a source and the source contacts adjacent the edge.

公开(公告)号：US20180203613A1

公开(公告)日：2018-07-19

申请号：US15408671

申请日：2017-01-18

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G06F3/06 ,  G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/1159 ,  H01L27/11597

CPC classification number: G06F3/0613 ,  G06F3/0625 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0679 ,  G11C11/005 ,  G11C11/5628 ,  G11C11/5657 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/3459 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/516

Abstract: Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a conductive line, non-volatile memory cells of a first memory cell type, the non-volatile memory cells coupled in series among each other, and an additional non-volatile memory cell of a second memory cell type coupled to the conductive line and coupled in series with the non-volatile memory cells of the first memory cell type. The second memory cell type is different from the first memory cell type.

公开(公告)号：US20180053552A1

公开(公告)日：2018-02-22

申请号：US15690497

申请日：2017-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa ,  Han Zhao

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each string of the plurality of strings is selectively connected to a common data line through a corresponding respective select gate. A first set of access lines are each coupled to a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. A second set of access lines are each coupled to a respective memory cell of each string of series-connected memory cells of only a portion of the plurality of strings of series-connected memory cells.

公开(公告)号：US20170372784A1

公开(公告)日：2017-12-28

申请号：US15692565

申请日：2017-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Ramin Ghodsi ,  Toru Tanzawa

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C16/26 ,  G11C16/12

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459

Abstract: Programming methods include applying a voltage to a selected access line commonly connected to a plurality of memory cells, and, while the voltage applied to the selected access line remains at a program voltage without being discharged, electrically connecting a subset of the plurality of memory cells to one data line so that only one memory cell of the subset of the plurality of memory cells is electrically connected to the one data line at a time.

公开(公告)号：US20170365298A1

公开(公告)日：2017-12-21

申请号：US15692512

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C5/06 ,  H01L27/11529 ,  H01L27/11524 ,  G11C16/26 ,  G11C7/12 ,  G11C5/02 ,  G11C7/22 ,  H01L27/11551 ,  G11C16/10 ,  G11C16/16 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C5/063 ,  G11C5/02 ,  G11C5/06 ,  G11C7/12 ,  G11C7/222 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11551

Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

公开(公告)号：US20170352426A1

公开(公告)日：2017-12-07

申请号：US15685909

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  G11C16/32

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/32

Abstract: Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated with a respective charge storage device of a string of charge storage devices. The electrical potential of a selected one of the access lines is lowered, and a data state of the charge storage device associated with the selected access line is sensed while the electrical potential of the selected access line is being lowered. Additional apparatus and methods are described.

公开(公告)号：US20170352421A1

公开(公告)日：2017-12-07

申请号：US15686416

申请日：2017-08-25

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G11C11/56

CPC classification number: G11C16/0483 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/26

Abstract: Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. The lower strings can include a third string of memory cells and a fourth string of memory cells arranged substantially parallel and adjacent to one another. The strings can each have a separate sense amplifier coupled thereto. The first and third strings and the second and fourth strings can be configured to be respectively coupled in series with each other during a read operation. Additional apparatuses and methods are described.

公开(公告)号：US20170309641A1

公开(公告)日：2017-10-26

申请号：US15645635

申请日：2017-07-10

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/11582 ,  H01L29/49 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11531 ,  H01L27/11529 ,  H01L27/11524 ,  H01L21/02 ,  G11C8/10

Abstract: Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.

公开(公告)号：US09780110B2

公开(公告)日：2017-10-03

申请号：US14828185

申请日：2015-08-17

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/1157 ,  G11C16/08 ,  G11C16/10 ,  G11C5/06

CPC classification number: H01L27/11582 ,  G11C5/063 ,  G11C16/08 ,  G11C16/10 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described.