公开(公告)号：US20050006675A1

公开(公告)日：2005-01-13

申请号：US10915805

申请日：2004-08-11

申请人： Yoshitaka Tsunashima ,  Seiji Ihumiya ,  Yasumasa Suizu ,  Yoshio Ozawa ,  Kiyotaka Miyano ,  Masayuki Tanaka

发明人： Yoshitaka Tsunashima ,  Seiji Ihumiya ,  Yasumasa Suizu ,  Yoshio Ozawa ,  Kiyotaka Miyano ,  Masayuki Tanaka

IPC分类号： H01L21/283 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/76 ,  H01L31/062 ,  B21D39/00 ,  H01L31/119

CPC分类号： H01L21/82345 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/31604 ,  H01L21/823462 ,  H01L21/823475 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656

摘要： Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.

摘要翻译： 权利要求和公开的是一种半导体器件，包括具有在包含金属，硅和氧的金属硅酸盐的化合物中含有氮或氟的栅极绝缘膜结构的晶体管，具有非晶态金属氧化物层叠结构的栅极绝缘膜结构 膜和金属硅酸盐膜，或具有包括第一金属元素的氧化物膜的第一栅极绝缘膜和包括第二金属元素的金属硅酸盐膜的第二栅极绝缘膜的栅极绝缘膜结构。

公开(公告)号：US07387934B2

公开(公告)日：2008-06-17

申请号：US11267331

申请日：2005-11-07

申请人： Yoshio Ozawa ,  Masayuki Tanaka ,  Fumitaka Arai

发明人： Yoshio Ozawa ,  Masayuki Tanaka ,  Fumitaka Arai

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7883

摘要： The memory cell matrix encompasses (a) a plurality device isolation films running along column direction, (b) first conductive layers arranged along row and column-directions, adjacent groups of the first conductive layers are isolated from each other by the device isolation film disposed between the adjacent groups, (c) lower inter-electrode dielectrics arranged respectively on crests of the corresponding first conductive layers, (d) an upper inter-electrode dielectric arranged on the lower inter-electrode dielectric made of insulating material different from the lower inter-electrode dielectrics, and (e) second conductive layers running along the row-direction, arranged on the upper inter-electrode dielectric.

摘要翻译： 存储单元矩阵包括（a）沿着列方向延伸的多个器件隔离膜，（b）沿着行和列方向布置的第一导电层，相邻的第一导电层组通过设置隔离膜彼此隔离 （c）分别布置在相应的第一导电层的顶部上的下部电极间电介质，（d）布置在由绝缘材料制成的下部电极间电介质上的上部电极间电介质， - 电极介质，和（e）布置在上部电极间电介质上的沿着行方向延伸的第二导电层。

公开(公告)号：US20070284652A1

公开(公告)日：2007-12-13

申请号：US11783141

申请日：2007-04-06

申请人： Takuya Kobayashi ,  Katsuyuki Sekine ,  Yoshio Ozawa ,  Masayuki Tanaka

发明人： Takuya Kobayashi ,  Katsuyuki Sekine ,  Yoshio Ozawa ,  Masayuki Tanaka

IPC分类号： H01L29/792

CPC分类号： H01L29/513 ,  H01L29/40117 ,  H01L29/517

摘要： A semiconductor memory device capable of suppressing detrapping of stored charges from a charge storage dielectric is disclosed. According to one aspect of the present invention, there is provided a semiconductor memory device comprising a semiconductor substrate, a blocking dielectric disposed on the semiconductor substrate a charge storage dielectric disposed on the blocking dielectric to store holes, a hole conductive dielectric disposed on the charge storage dielectric, and a gate electrode disposed on the hole conductive dielectric.

摘要翻译： 公开了能够抑制存储电荷从电荷存储电介质中去除的半导体存储器件。 根据本发明的一个方面，提供了一种半导体存储器件，其包括半导体衬底，设置在半导体衬底上的阻挡电介质，设置在阻挡电介质上以存储孔的电荷存储电介质，设置在电荷上的导电电介质 存储电介质和设置在导电电介质上的栅电极。

公开(公告)号：US20070215958A1

公开(公告)日：2007-09-20

申请号：US11798593

申请日：2007-05-15

申请人： Masayuki Tanaka ,  Yoshio Ozawa ,  Shigehiko Saida ,  Akira Goda ,  Mitsuhiro Noguchi ,  Yuichiro Mitani ,  Yoshitaka Tsunashima

发明人： Masayuki Tanaka ,  Yoshio Ozawa ,  Shigehiko Saida ,  Akira Goda ,  Mitsuhiro Noguchi ,  Yuichiro Mitani ,  Yoshitaka Tsunashima

IPC分类号： H01L29/94

CPC分类号： H01L21/022 ,  H01L21/0217 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/3185 ,  H01L21/76838 ,  H01L21/76897 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/792

摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.

摘要翻译： 公开了一种半导体器件，包括半导体衬底，栅电极，形成在半导体衬底和栅电极之间的第一绝缘膜，以及沿着栅电极的顶表面或侧表面形成的第二绝缘膜， 包含氮，硅和氢的氮化硅膜和形成在下部氮化硅膜上并含有氮，硅和氢的上部氮化硅膜，并且其中氮（N）与硅（Si）的组成比N / Si在 下氮化硅膜比上述氮化硅膜高。

公开(公告)号：US07148158B2

公开(公告)日：2006-12-12

申请号：US10916500

申请日：2004-08-12

申请人： Yoshio Ozawa ,  Masayuki Tanaka ,  Kiyotaka Miyano ,  Shigehiko Saida

发明人： Yoshio Ozawa ,  Masayuki Tanaka ,  Kiyotaka Miyano ,  Shigehiko Saida

IPC分类号： H01L21/338 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L29/4983 ,  H01L29/41783 ,  H01L29/6656

摘要： A semiconductor device includes a semiconductor device comprising a semiconductor substrate, source/drain regions formed in the semiconductor substrate, a gate insulation film formed on the semiconductor substrate, a gate electrode formed on the gate insulation film between the source/drain regions, and a gate sidewall spacer formed on side surfaces of the gate electrode, wherein the gate sidewall spacer is composed of silicon oxide containing 0.1–30 atomic % of chlorine.

公开(公告)号：US20050003619A1

公开(公告)日：2005-01-06

申请号：US10717719

申请日：2003-11-21

申请人： Masayuki Tanaka ,  Atsuhiro Sato ,  Hiroki Yamashita ,  Ichiro Mizushima ,  Yoshio Ozawa

发明人： Masayuki Tanaka ,  Atsuhiro Sato ,  Hiroki Yamashita ,  Ichiro Mizushima ,  Yoshio Ozawa

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

摘要： A semiconductor memory encompasses a memory cell matrix, which embraces device isolation films running along the column-direction, arranged alternatively between the cell columns; first conductive layers having top surfaces lower than the device isolation films; inter-electrode dielectrics arranged on the corresponding first conductive layers, the inter-electrode dielectric has a dielectric constant larger than that of silicon oxide; and second conductive layers running along the row-direction, each of the second conductive layers arranged on the inter-electrode dielectric and the device isolation films so that the second conductive layer can be shared by the memory cell transistors arranged along the row-direction belonging to different cell columns.

摘要翻译： 半导体存储器包括存储单元矩阵，其包括沿列方向延伸的器件隔离膜，交替地布置在单元列之间; 第一导电层的顶表面低于器件隔离膜; 布置在相应的第一导电层上的电极间电介质，所述电极间电介质的介电常数大于氧化硅的介电常数; 和沿着行方向延伸的第二导电层，每个第二导电层布置在电极间电介质和器件隔离膜上，使得第二导电层可以被沿着行方向归属布置的存储单元晶体管共享 到不同的细胞柱。

公开(公告)号：US20090233451A1

公开(公告)日：2009-09-17

申请号：US12471830

申请日：2009-05-26

申请人： Yoshitaka Tsunashima ,  Seiji Ihumiya ,  Yasumasa Suizu ,  Yoshio Ozawa ,  Kiyotaka Miyano ,  Masayuki Tanaka

发明人： Yoshitaka Tsunashima ,  Seiji Ihumiya ,  Yasumasa Suizu ,  Yoshio Ozawa ,  Kiyotaka Miyano ,  Masayuki Tanaka

IPC分类号： H01L21/31

CPC分类号： H01L21/82345 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/31604 ,  H01L21/823462 ,  H01L21/823475 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656

摘要： Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.

摘要翻译： 权利要求和公开的是一种半导体器件，包括具有在包含金属，硅和氧的金属硅酸盐的化合物中含有氮或氟的栅极绝缘膜结构的晶体管，具有非晶态金属氧化物层叠结构的栅极绝缘膜结构 膜和金属硅酸盐膜，或具有包括第一金属元素的氧化物膜的第一栅极绝缘膜和包括第二金属元素的金属硅酸盐膜的第二栅极绝缘膜的栅极绝缘膜结构。

公开(公告)号：US07372113B2

公开(公告)日：2008-05-13

申请号：US10880508

申请日：2004-07-01

申请人： Masayuki Tanaka ,  Yoshio Ozawa ,  Shigehiko Saida ,  Akira Goda ,  Mitsuhiro Noguchi ,  Yuichiro Mitani ,  Yoshitaka Tsunashima

发明人： Masayuki Tanaka ,  Yoshio Ozawa ,  Shigehiko Saida ,  Akira Goda ,  Mitsuhiro Noguchi ,  Yuichiro Mitani ,  Yoshitaka Tsunashima

IPC分类号： H01L21/314

CPC分类号： H01L21/022 ,  H01L21/0217 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3185 ,  H01L21/76838 ,  H01L21/76897 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/792

摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.

摘要翻译： 公开了一种半导体器件，包括半导体衬底，栅电极，形成在半导体衬底和栅电极之间的第一绝缘膜，以及沿着栅电极的顶表面或侧表面形成的第二绝缘膜， 包含氮，硅和氢的氮化硅膜和形成在下部氮化硅膜上并含有氮，硅和氢的上部氮化硅膜，并且其中氮（N）与硅（Si）的组成比N / Si在 下氮化硅膜比上述氮化硅膜高。

公开(公告)号：US20070183208A1

公开(公告)日：2007-08-09

申请号：US11653278

申请日：2007-01-16

申请人： Masayuki Tanaka ,  Ryota Fujitsuka ,  Katsuyuki Sekine ,  Yoshio Ozawa ,  Daisuke Nishida

发明人： Masayuki Tanaka ,  Ryota Fujitsuka ,  Katsuyuki Sekine ,  Yoshio Ozawa ,  Daisuke Nishida

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/0483 ,  G11C16/3427 ,  G11C16/3454

摘要： A plurality of memory cell transistors each of which has a gate structure having a floating gate electrode formed of a first conductive film and stacked on an element region surrounded by an element isolation region on a silicon substrate with a first insulating film disposed therebetween and a control gate electrode formed of a second conductive film and stacked on the first conductive film with a second insulating film with a large dielectric constant disposed therebetween are arranged in a memory cell array. A detrap pulse supply circuit generates and supplies a detrap pulse signal to the control gate electrode of the memory cell transistor to extract charges from the second insulating film after data is written into each of the memory cell transistors.

摘要翻译： 多个存储单元晶体管，每个存储单元晶体管具有栅极结构，该栅极结构具有由第一导电膜形成并浮置在由硅衬底上的元件隔离区域围绕的元件区域上的浮置栅电极，其间设置有第一绝缘膜， 在存储单元阵列中布置由第二导电膜形成的层叠在具有介电常数大的第二绝缘膜的第一导电膜上的栅电极。 去除脉冲电源电路产生并提供去除脉冲信号到存储单元晶体管的控制栅电极，以便在将数据写入每个存储单元晶体管之后从第二绝缘膜提取电荷。

公开(公告)号：US20060054957A1

公开(公告)日：2006-03-16

申请号：US11267334

申请日：2005-11-07

申请人： Yoshio Ozawa ,  Masayuki Tanaka ,  Fumitaka Arai

发明人： Yoshio Ozawa ,  Masayuki Tanaka ,  Fumitaka Arai

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7883

摘要： The memory cell matrix encompasses (a) a plurality device isolation films running along column direction, (b) first conductive layers arranged along row and column-directions, adjacent groups of the first conductive layers are isolated from each other by the device isolation film disposed between the adjacent groups, (c) lower inter-electrode dielectrics arranged respectively on crests of the corresponding first conductive layers, (d) an upper inter-electrode dielectric arranged on the lower inter-electrode dielectric made of insulating material different from the lower inter-electrode dielectrics, and (e) second conductive layers running along the row-direction, arranged on the upper inter-electrode dielectric.

摘要翻译： 存储单元矩阵包括（a）沿着列方向延伸的多个器件隔离膜，（b）沿着行和列方向布置的第一导电层，相邻的第一导电层组通过设置的隔离膜相互隔离 （c）分别布置在相应的第一导电层的顶部上的下部电极间电介质，（d）布置在由绝缘材料制成的下部电极间电介质上的上部电极间电介质， - 电极介质，和（e）布置在上部电极间电介质上的沿着行方向延伸的第二导电层。