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    Host controlled enablement of automatic background operations in a memory device
    61.
    发明授权
    Host controlled enablement of automatic background operations in a memory device 有权
    主机控制启用自动后台操作在存储设备中

    公开(公告)号：US09329990B2

    公开(公告)日：2016-05-03

    申请号：US13739453

    申请日：2013-01-11

    Applicant: Micron Technology, Inc.

    Inventor： Francesco Falanga ,  Danilo Caraccio

    IPC: G06F12/00 ,  G06F12/02

    CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0246 ,  G06F2212/7211

    Abstract: A host that is coupled to a memory device is configured to read a status register of the memory device to determine if the memory device supports host controlled enablement of automatic background operations. The memory device responds to the host regarding whether the memory device supports host controlled enablement of automatic background operations. The host can enable the automatic background operations if the memory device supports this feature. The host can then set a time period in the memory device that is indicative of when the memory device can automatically perform the background operations.

    Abstract translation: 耦合到存储设备的主机被配置为读取存储器设备的状态寄存器以确定存储器设备是否支持主机控制的自动后台操作的启用。 存储器设备响应于主机是否支持主机控制启用自动后台操作。 如果内存设备支持此功能，主机可以启用自动后台操作。 然后，主机可以在存储器设备中设置指示存储器设备何时可以自动执行后台操作的时间段。

    COMMAND QUEUING
    62.
    发明申请
    COMMAND QUEUING 有权
    指挥队伍

    公开(公告)号：US20150234601A1

    公开(公告)日：2015-08-20

    申请号：US14181089

    申请日：2014-02-14

    Applicant: Micron Technology, Inc.

    Inventor： Victor Y. Tsai ,  Danilo Caraccio ,  Daniele Balluchi ,  Neal A. Galbo ,  Robert Warren

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0679 ,  G06F3/0688

    Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

    Abstract translation: 本公开包括用于命令排队的装置和方法。 许多实施例包括从主机在存储器系统处接收排队的命令请求，从存储器系统向主机发送指示存储器系统准备好在存储器系统的命令队列中接收命令的命令响应，以及 响应于发送命令响应，从所述主机接收在所述存储器系统处的所述命令的命令描述符块。

    SECURITY MANAGEMENT OF FERROELECTRIC MEMORY DEVICE
    64.
    发明申请
    SECURITY MANAGEMENT OF FERROELECTRIC MEMORY DEVICE 有权

    公开(公告)号：US20250148133A1

    公开(公告)日：2025-05-08

    申请号：US19013585

    申请日：2025-01-08

    Applicant: Micron Technology, Inc.

    Inventor： Danilo Caraccio ,  Federica Cresci ,  Alessandro Orlando ,  Paolo Amato ,  Angelo Alberto Rovelli ,  Craig A. Jones ,  Niccolò Izzo

    IPC: G06F21/79 ,  G06F21/10 ,  G06F21/55 ,  G06F21/60 ,  G11C11/22

    Abstract: Systems, apparatuses, and methods related to security management for a ferroelectric memory device are described. An example method can include receiving, at a memory controller and from a host, a command and firmware data. The memory controller can manage a non-volatile memory device, such as a ferroelectric memory device, and the host and the memory controller can communicate using a compute express link (CXL) protocol. The command can be executed to update firmware stored on the non-volatile memory device. The method can further include accessing a first public key from the non-volatile memory device. The method can further include validating the first public key with a second public key within the firmware data. The method can further include validating the firmware data. The method can further include verifying a security version of the firmware data. The method can further include updating the non-volatile memory device with the firmware data.

    DUAL COMPRESSION IN MEMORY DEVICES
    65.
    发明申请
    DUAL COMPRESSION IN MEMORY DEVICES 有权

    公开(公告)号：US20250094047A1

    公开(公告)日：2025-03-20

    申请号：US18782539

    申请日：2024-07-24

    Applicant: Micron Technology, Inc.

    Inventor： Marco Sforzin ,  Rishabh Dubey ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri ,  Nicola Del Gatto

    IPC: G06F3/06

    Abstract: A variety of applications can include a memory device implementing a dual compression scheme. A memory subsystem of the memory device can be arranged into multiple regions. A first region of the memory subsystem can be used to store non-compressible data. A second region can be used to store compressible data. The second region can have a first subregion and a second subregion. The first subregion can be used to accept compressible data as non-compressed data corresponding to a compression ratio being less than a threshold compression ratio. The second subregion can be used to accept compressed data corresponding to a compression ratio being greater than the threshold compression ratio. Additional apparatus, systems, and methods are disclosed.

    ROW HAMMER TELEMETRY
    66.
    发明申请
    ROW HAMMER TELEMETRY 有权

    公开(公告)号：US20250053343A1

    公开(公告)日：2025-02-13

    申请号：US18929332

    申请日：2024-10-28

    Applicant: Micron Technology, Inc.

    Inventor： Amitava Majumdar ,  Anandhavel Nagendrakumar ,  Mohammed Ebrahim Hargan ,  Scott Garner ,  Danilo Caraccio ,  Daniele Balluchi ,  Chia Wei Chang ,  Ankush Lal

    IPC: G06F3/06 ,  G11C11/406

    Abstract: An apparatus can include a number of memory devices and a memory controller coupled to one or more of the number of memory devices. The memory controller can include a row hammer detector. The memory controller can be configured increment for a first time period a row counter in a first data structure and a refresh counter. The memory controller can be configured to increment for a second time period a row counter in a second data structure and the refresh counter. The memory controller can be configured to determine that a value of the refresh counter exceeds a refresh threshold and responsive to the determination that the value of the refresh counter exceeds the refresh threshold, issue a notification.

    Techniques for managing offline identity upgrades
    68.
    发明授权
    Techniques for managing offline identity upgrades 有权

    公开(公告)号：US12124833B2

    公开(公告)日：2024-10-22

    申请号：US17744350

    申请日：2022-05-13

    Applicant: Micron Technology, Inc.

    Inventor： Niccolo Izzo ,  Alessandro Orlando ,  Danilo Caraccio ,  David Hulton

    IPC: G06F8/65 ,  H04L9/08

    CPC classification number: G06F8/65 ,  H04L9/088

    Abstract: Methods, systems, and devices for techniques for managing offline identity upgrades are described. A memory system may receive a command to update a device identifier for a device identifier composition engine (DICE) associated with the memory system. The memory system may generate an updated device identifier, at a first software layer of a set of software layers of the DICE, based on receiving the command. The memory system may decrypt a device specific key (DSK) stored at a read-only memory device of the memory system based on the received command, and sign the updated device identifier using the DSK based on decrypting the DSK. The memory system may execute one or more operations associated with the first software layer of the set of software layers of the DICE based on the signed updated device identifier.

    GLITCH DETECTION
    70.
    发明公开
    GLITCH DETECTION 审中-公开

    公开(公告)号：US20240185938A1

    公开(公告)日：2024-06-06

    申请号：US18516121

    申请日：2023-11-21

    Applicant: Micron Technology, Inc.

    Inventor： Niccolò Izzo ,  David Hulton ,  Tamara Schmitz ,  Angelo Alberto Rovelli ,  Craig A. Jones ,  Danilo Caraccio

    IPC: G11C29/08 ,  G11C29/02

    CPC classification number: G11C29/08 ,  G11C29/023

    Abstract: A method can include performing at least one glitch resistance operation and detecting, by a circuit included in a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. The method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. The method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.

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