公开(公告)号：US20230123487A1

公开(公告)日：2023-04-20

申请号：US18083445

申请日：2022-12-16

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Haitao Liu ,  Vladimir Mikhalev

IPC: H01L23/528 ,  H01L29/78 ,  H10B10/00 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

Abstract: A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.

公开(公告)号：US11374132B2

公开(公告)日：2022-06-28

申请号：US17087842

申请日：2020-11-03

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L29/94 ,  G11C16/30 ,  H01L29/49 ,  H01L21/28 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/66 ,  G11C16/04

Abstract: A semiconductor structure includes a capacitor structure comprising an active region comprising opposing field edges parallel to a first horizontal direction and a gate region comprising opposing gate edges parallel to a second horizontal direction transverse to the first horizontal direction. The semiconductor structure also comprises a first dielectric material adjacent at least one of the opposing field edges or the opposing gate edges and a second dielectric material adjacent the active area and abutting portions of the first dielectric material. A height of the second dielectric material in a vertical direction may be less than the height of the first dielectric material. Semiconductor devices and related methods are also disclosed.

公开(公告)号：US10978474B2

公开(公告)日：2021-04-13

申请号：US16553587

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Roger W. Lindsay ,  Michael A. Smith ,  Brett D. Lowe

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/768 ,  H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11524 ,  H01L27/1157

Abstract: A method of forming a semiconductor device structure comprises forming a stack structure comprising stacked tiers. Each of the stacked tiers comprises a first structure comprising a first material and a second structure comprising a second, different material longitudinally adjacent the first structure. A patterned hard mask structure is formed over the stack structure. Dielectric structures are formed within openings in the patterned hard mask structure. A photoresist structure is formed over the dielectric structures and the patterned hard mask structure. The photoresist structure, the dielectric structures, and the stack structure are subjected to a series of material removal processes to form apertures extending to different depths within the stack structure. Dielectric structures are formed over side surfaces of the stack structure within the apertures. Conductive contact structures are formed to longitudinally extend to bottoms of the apertures. Semiconductor device structures, semiconductor devices, and electronic systems are also described.

公开(公告)号：US20190096906A1

公开(公告)日：2019-03-28

申请号：US16183392

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Roger W. Lindsay ,  Michael A. Smith ,  Brett D. Lowe

IPC: H01L27/11582 ,  H01L27/11575 ,  H01L27/11524 ,  H01L21/033 ,  H01L21/027 ,  H01L27/11556 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A method of forming a semiconductor device structure comprises forming a stack structure comprising stacked tiers. Each of the stacked tiers comprises a first structure comprising a first material and a second structure comprising a second, different material longitudinally adjacent the first structure. A patterned hard mask structure is formed over the stack structure. Dielectric structures are formed within openings in the patterned hard mask structure. A photoresist structure is formed over the dielectric structures and the patterned hard mask structure. The photoresist structure, the dielectric structures, and the stack structure are subjected to a series of material removal processes to form apertures extending to different depths within the stack structure. Dielectric structures are formed over side surfaces of the stack structure within the apertures. Conductive contact structures are formed to longitudinally extend to bottoms of the apertures. Semiconductor device structures, semiconductor devices, and electronic systems are also described.

公开(公告)号：US20180342530A1

公开(公告)日：2018-11-29

申请号：US15606415

申请日：2017-05-26

Applicant: Micron Technology, Inc.

Inventor： Roger W. Lindsay ,  Michael A. Smith ,  Brett D. Lowe

IPC: H01L27/11582 ,  H01L21/033 ,  H01L21/027 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11556

Abstract: A method of forming a semiconductor device structure comprises forming a stack structure comprising stacked tiers. Each of the stacked tiers comprises a first structure comprising a first material and a second structure comprising a second, different material longitudinally adjacent the first structure. A patterned hard mask structure is formed over the stack structure. Dielectric structures are formed within openings in the patterned hard mask structure. A photoresist structure is formed over the dielectric structures and the patterned hard mask structure. The photoresist structure, the dielectric structures, and the stack structure are subjected to a series of material removal processes to form apertures extending to different depths within the stack structure. Dielectric structures are formed over side surfaces of the stack structure within the apertures. Conductive contact structures are formed to longitudinally extend to bottoms of the apertures. Semiconductor device structures, semiconductor devices, and electronic systems are also described.

公开(公告)号：US10020228B2

公开(公告)日：2018-07-10

申请号：US15357602

申请日：2016-11-21

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L21/8234 ,  H01L27/092 ,  H01L27/088 ,  H01L27/085 ,  H01L27/06 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L27/02 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/08 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11529 ,  H01L27/11531

CPC classification number: H01L21/823418 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/0207 ,  H01L27/0617 ,  H01L27/085 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11573 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0873 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/788 ,  H01L29/792

Abstract: Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped.

公开(公告)号：US09870990B2

公开(公告)日：2018-01-16

申请号：US15288522

申请日：2016-10-07

Applicant: Micron Technology, Inc.

Inventor： Eric H. Freeman ,  Michael A. Smith

IPC: H01L29/76 ,  H01L23/528 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L23/528 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/76892 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.

公开(公告)号：US09466531B2

公开(公告)日：2016-10-11

申请号：US14679488

申请日：2015-04-06

Applicant: Micron Technology, Inc.

Inventor： Eric H. Freeman ,  Michael A. Smith

IPC: H01L29/76 ,  H01L21/768 ,  H01L27/115 ,  H01L23/528 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L23/528 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/76892 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.

公开(公告)号：US09236307B2

公开(公告)日：2016-01-12

申请号：US14702571

申请日：2015-05-01

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/088 ,  H01L27/115 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L21/823418 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/0207 ,  H01L27/0617 ,  H01L27/085 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11573 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0873 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/788 ,  H01L29/792

Abstract: Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped.

Abstract translation: 一些实施例包括具有第一和第二晶体管的集成电路 第一晶体管比第二晶体管宽。 第一和第二晶体管分别具有第一和第二有源区。 电介质特征与第一有源区相关联并且分解第一有源区。 第二活性区域不会分解成与第一活性区域相同的程度。 一些实施例包括形成晶体管的方法。 形成第一和第二晶体管的有源区。 第一晶体管的有效面积比第二晶体管的有效面积宽。 电介质特征形成在第一晶体管的有源区中。 第一晶体管的有效面积被分解为与第二晶体管的有效面积不同的程度。 第一和第二晶体管的有源区同时掺杂。

公开(公告)号：US09171903B2

公开(公告)日：2015-10-27

申请号：US13897112

申请日：2013-05-17

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/1033 ,  H01L29/0653 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7835

Abstract: Some embodiments include transistors having a channel region under a gate, having a source/drain region laterally spaced from the channel region by an active region, and having one or more dielectric features extending through the active region in a configuration which precludes any straight-line lateral conductive path from the channel region to the source/drain region. The dielectric features may be spaced-apart islands in some configurations. The dielectric features may be multi-branched interlocking structures in some configurations.

Abstract translation: 一些实施例包括在栅极下方具有沟道区的晶体管，其源极/漏极区域与沟道区域横向间隔有效区域，并且具有延伸穿过有源区域的一个或多个介电特征，排除了任何直线 从沟道区到源极/漏极区的横向导电路径。 在一些配置中，电介质特征可以是间隔开的岛。 介电特征可以是一些配置中的多分支互锁结构。