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    MEMORY CONSTRUCTIONS
    64.
    发明申请
    MEMORY CONSTRUCTIONS 有权
    记忆结构

    公开(公告)号：US20140110657A1

    公开(公告)日：2014-04-24

    申请号：US13658676

    申请日：2012-10-23

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Andrea Redaelli ,  Agostino Pirovano

    IPC: H01L45/00

    CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/00 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144

    Abstract: Some embodiments include memory constructions having a plurality of bands between top and bottom electrically conductive materials. The bands include chalcogenide bands alternating with non-chalcogenide bands. In some embodiments, there may be least two of the chalcogenide bands and at least one of the non-chalcogenide bands. In some embodiments, the memory cells may be between a pair of electrodes; with one of the electrodes being configured as a lance, angled plate, container or beam. In some embodiments, the memory cells may be electrically coupled with select devices, such as, for example, diodes, field effect transistors or bipolar junction transistors.

    Abstract translation: 一些实施例包括在顶部和底部导电材料之间具有多个带的记忆结构。 这些带包括与非硫属化物带交替的硫属化物带。 在一些实施方案中，可以存在至少两个硫族化物带和至少一个非硫族化物带。 在一些实施例中，存储器单元可以在一对电极之间; 其中一个电极被配置为喷枪，倾斜板，容器或梁。 在一些实施例中，存储器单元可以与诸如二极管，场效应晶体管或双极结型晶体管的选择器件电耦合。

    SELF-SELECTING MEMORY ARRAY WITH HORIZONTAL ACCESS LINES
    65.
    发明申请
    SELF-SELECTING MEMORY ARRAY WITH HORIZONTAL ACCESS LINES 有权

    公开(公告)号：US20250061943A1

    公开(公告)日：2025-02-20

    申请号：US18814164

    申请日：2024-08-23

    Applicant: Micron Technology, Inc.

    Inventor： Lorenzo Fratin ,  Fabio Pellizzer ,  Agostino Pirovano ,  Russell L. Meyer

    IPC: G11C13/00 ,  H01L23/528

    Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material. Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.

    Techniques to manufacture ferroelectric memory devices
    66.
    发明授权
    Techniques to manufacture ferroelectric memory devices 有权

    公开(公告)号：US12211538B2

    公开(公告)日：2025-01-28

    申请号：US18203877

    申请日：2023-05-31

    Applicant: Micron Technology, Inc.

    Inventor： Giorgio Servalli ,  Marcello Mariani ,  Agostino Pirovano

    IPC: G11C11/22 ,  G11C5/06 ,  H01L29/51 ,  H10B53/10 ,  H10B53/20

    Abstract: Methods, systems, and devices for techniques to manufacture ferroelectric memory devices are described. In some cases, a memory array may be manufactured using a self-aligned manufacturing technique. For example, a continuous layer of dielectric material may be formed over an assembly which includes an array of transistors coupling contacts on the surface of the assembly with a set of digit lines. In some cases, an array of cavities may be etched into the dielectric material, each cavity exposing a set of contacts. A set of bottom electrodes corresponding to the set of contacts may be formed on sidewalls in each cavity, for example by depositing a layer of electrode material and etching the electrode material using a variety of hard masks.

    READING A MULTI-LEVEL MEMORY CELL
    67.
    发明公开
    READING A MULTI-LEVEL MEMORY CELL 审中-公开

    公开(公告)号：US20240321347A1

    公开(公告)日：2024-09-26

    申请号：US18643126

    申请日：2024-04-23

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Robustelli ,  Fabio Pellizzer ,  Innocenzo Tortorelli ,  Agostino Pirovano

    IPC: G11C11/56 ,  G11C7/10

    CPC classification number: G11C11/56 ,  G11C7/1051 ,  G11C7/1096

    Abstract: Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.

    VERTICAL MEMORY ARCHITECTURE
    70.
    发明公开
    VERTICAL MEMORY ARCHITECTURE 审中-公开

    公开(公告)号：US20230262995A1

    公开(公告)日：2023-08-17

    申请号：US17651217

    申请日：2022-02-15

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Fabio Pellizzer

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/249 ,  H01L27/2454 ,  H01L45/06 ,  H01L45/1683

    Abstract: Methods, systems, and devices for a vertical memory architecture are described. A memory device may include memory cells arranged in a three-dimensional vertical memory architecture. Each memory cell may include a storage element (e.g., a chalcogenide material), where a logic state may be programmed at the storage element based on a polarity of an applied voltage that exceeds a threshold voltage. The storage element may be coupled with a selection element and a conductive line. The selection element may be coupled with a bit line decoder and a word line decoder via vertical pillars. The selection element may selectively couple the storage element with the bit line decoder. In some examples, an activation voltage for the selection element may be less than a threshold voltage of the storage element.

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