公开(公告)号：US20220130954A1

公开(公告)日：2022-04-28

申请号：US17078755

申请日：2020-10-23

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Harsh Narendrakumar Jain

IPC: H01L29/06 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, a staircase structure within the stack structure having steps comprising horizontal edges of the tiers, a first insulative material vertically overlying the staircase structure, conductive contact structures comprising a conductive material extending through the first insulative material and in contact with the steps of the staircase structure, and a second insulative material extending in a first horizontal direction between horizontally neighboring conductive contact structures and exhibiting one or more different properties than the first insulative material. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20220108998A1

公开(公告)日：2022-04-07

申请号：US17063101

申请日：2020-10-05

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Indra V. Chary

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one slit region divides the stack structure into blocks. Each block comprises an array of active pillars. Along the at least one slit region is a horizontally alternating sequence of slit structure segments and support pillar structures. The slit structure segments and the support pillar structures each extend vertically through the stack structure. Additional microelectronic devices are also disclosed as are related methods and electronic systems.

公开(公告)号：US20220068956A1

公开(公告)日：2022-03-03

申请号：US17008130

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Shawn D. Lyonsmith ,  Matthew J. King ,  Lisa M. Clampitt ,  John Hopkins ,  Kevin Y. Titus ,  Indra V. Chary ,  Martin Jared Barclay ,  Anilkumar Chandolu ,  Pavithra Natarajan ,  Roger W. Lindsay

IPC: H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11565

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.

公开(公告)号：US20210375894A1

公开(公告)日：2021-12-02

申请号：US17395751

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Justin B. Dorhout ,  Rita J. Klein

IPC: H01L27/11529 ,  G11C5/06 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11556

Abstract: Some embodiments include an integrated assembly having a conductive expanse over conductive nodes. The conductive nodes include a first composition. A bottom surface of the conductive expanse includes a second composition which is different composition than the first composition. A stack is over the conductive expanse. The stack includes alternating first and second levels. Pillar structures extend vertically through the stack. Each of the pillar structures includes a post of conductive material laterally surrounded by an insulative liner. At least one of the posts extends through the conductive expanse to directly contact one of the conductive nodes. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20200373316A1

公开(公告)日：2020-11-26

申请号：US16422150

申请日：2019-05-24

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Justin B. Dorhout ,  Rita J. Klein

IPC: H01L27/11529 ,  G11C5/06 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: Some embodiments include an integrated assembly having a conductive expanse over conductive nodes. The conductive nodes include a first composition. A bottom surface of the conductive expanse includes a second composition which is different composition than the first composition. A stack is over the conductive expanse. The stack includes alternating first and second levels. Pillar structures extend vertically through the stack. Each of the pillar structures includes a post of conductive material laterally surrounded by an insulative liner. At least one of the posts extends through the conductive expanse to directly contact one of the conductive nodes. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20180286879A1

公开(公告)日：2018-10-04

申请号：US16002129

申请日：2018-06-07

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Matthew Park ,  Joseph Neil Greeley ,  Chet E. Carter ,  Martin C. Roberts ,  Indra V. Chary ,  Vinayak Shamanna ,  Ryan Meyer ,  Paolo Tessariol

IPC: H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11519

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region. Conductive vias extend elevationally through the vertically-alternating tiers in the second region. An elevationally-extending wall is laterally between the first and second regions. The wall comprises the programmable charge storage material and the semiconductive channel material. Other embodiments and aspects, including method, are disclosed.

公开(公告)号：US12213317B2

公开(公告)日：2025-01-28

申请号：US18508875

申请日：2023-11-14

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  Justin B. Dorhout ,  Jian Li ,  Haitao Liu ,  Paolo Tessariol

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The operative channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. An elevationally-extending wall is in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane. Other embodiments, including method are disclosed.

公开(公告)号：US20240355363A1

公开(公告)日：2024-10-24

申请号：US18630919

申请日：2024-04-09

Applicant: Micron Technology, Inc.

Inventor： Mithun Kumar Ramasahayam ,  Indra V. Chary ,  Meng-Wei Kuo

IPC: G11C5/06 ,  G11C16/04 ,  H01L29/49 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C5/063 ,  G11C16/0483 ,  H01L29/4966 ,  H10B43/27 ,  H10B43/35

Abstract: Methods, systems, and devices for a bit line contact scheme in a memory system stack are described. A memory architecture may include bit lines coupled with bit line contacts, and pillars coupled with circuitry associated with supporting operation of the bit lines. Hybrid plugs may be integrated into the pillars to couple the bit line contacts with the pillars, forming a conductive path between the bit lines and the circuitry. The hybrid plugs may be recessed within the pillars such that the hybrid plugs do not extend through the memory architecture beyond the pillars. The hybrid plugs may include one or more relatively low capacitance, conductive materials, such as a titanium alloy material (e.g., titanium, titanium nitride), a tungsten alloy material (e.g., tungsten, tungsten nitride), or any combination thereof, among other materials.

公开(公告)号：US20240347464A1

公开(公告)日：2024-10-17

申请号：US18752525

申请日：2024-06-24

Applicant: Micron Technology, Inc.

Inventor： Lingyu Kong ,  Lifang Xu ,  Indra V. Chary ,  Shuangqiang Luo ,  Sok Han Wong

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/562 ,  H10B41/27 ,  H10B43/27

Abstract: A microelectronic device comprises a stack structure comprising insulative structures vertically interleaved with conductive structures, first support pillar structures vertically extending through the stack structure in a first staircase region including steps defined at edges of tiers of the insulative structures and conductive structures, and second support pillar structures vertically extending through the stack structure in a second staircase region including additional steps defined at edges of additional tiers of the insulative structures and conductive structures, the second support pillar structures having a smaller cross-sectional area than the first support pillar structures. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20240341095A1

公开(公告)日：2024-10-10

申请号：US18602321

申请日：2024-03-12

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Kar Wui Thong

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: Memory circuitry comprising strings of memory cells comprises vertically-alternating insulative tiers and conductive tiers that extend from a memory-array region into a stair-step region across an intermediate region that is between the memory-array region and the stair-step region. The insulative tiers and the conductive tiers comprise memory blocks upper portions of which individually comprise sub-blocks. Sub-block trenches are in the upper portions individually between immediately-laterally-adjacent of the sub-blocks. Strings of memory cells in the memory-array region comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks and in the sub-blocks. The sub-block trenches in the memory-array region, in the intermediate region, and in the stair-step region individually have a top. The top of individual of the sub-block trenches in the stair-step region has a narrowest-width that is larger than a narrowest-width of the top of the individual sub-block trenches in the intermediate region. The narrowest-width of the top of the individual sub-block trenches in the intermediate region is larger than a narrowest-width of the top of the individual sub-block trenches in the memory-array region. Other embodiments, including method, are disclosed.