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    FPGA architecture at conventional and submicron scales
    61.
    发明授权
    FPGA architecture at conventional and submicron scales 有权
    常规和亚微米尺度的FPGA架构

    公开(公告)号：US07405462B2

    公开(公告)日：2008-07-29

    申请号：US11343304

    申请日：2006-01-31

    申请人： Gregory S. Snider ,  Philip J. Kuekes

    发明人： Gregory S. Snider ,  Philip J. Kuekes

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17748 ,  B82Y10/00 ,  B82Y30/00 ,  G11C8/10 ,  G11C13/0007 ,  G11C13/0014 ,  G11C2213/15 ,  G11C2213/34 ,  G11C2213/51 ,  G11C2213/77 ,  G11C2213/81 ,  H03K19/17728 ,  H03K19/1778

    摘要： Reconfigurable logic devices and methods of programming the devices are disclosed. The logic device includes a look-up table (LUT) and at least one storage element configured for sampling LUT output signals. The LUT comprises a plurality of input signals, an array of programmable impedance devices operably coupled to the input signals, and the LUT output signals. Each programmable impedance device in the array includes a first electrode operably coupled to one of the input signal, a second electrode disposed to form a junction wherein the second electrode at least partially overlaps the first electrode, and a programmable material disposed between the first electrode and the second electrode. The programmable material operably couples the first electrode and the second electrode such that each programmable impedance device exhibits a non-volatile programmable impedance. The array may be configured as a one-dimensional or two-dimensional array.

    摘要翻译： 公开了可重构逻辑器件和编程器件的方法。 逻辑器件包括查找表（LUT）和配置用于对LUT输出信号进行采样的至少一个存储元件。 LUT包括多个输入信号，可操作地耦合到输入信号的可编程阻抗装置的阵列和LUT输出信号。 阵列中的每个可编程阻抗器件包括可操作地耦合到输入信号中的一个的第一电极，设置成形成其中第二电极至少部分地与第一电极重叠的结的第二电极和设置在第一电极和 第二电极。 可编程材料可操作地耦合第一电极和第二电极，使得每个可编程阻抗装置呈现非易失性可编程阻抗。 该阵列可以被配置为一维或二维阵列。

    Nanoscale latches and impedance-encoded logic for use in nanoscale state machines, nanoscale pipelines, and in other nanoscale electronic circuits
    64.
    发明授权
    Nanoscale latches and impedance-encoded logic for use in nanoscale state machines, nanoscale pipelines, and in other nanoscale electronic circuits 有权
    纳米尺度锁存器和阻抗编码逻辑，用于纳米级状态机，纳米级管道和其他纳米级电子电路

    公开(公告)号：US07242215B2

    公开(公告)日：2007-07-10

    申请号：US10974660

    申请日：2004-10-27

    申请人： Gregory S. Snider ,  Philip J. Kuekes

    发明人： Gregory S. Snider ,  Philip J. Kuekes

    IPC分类号： H03K19/173

    CPC分类号： B82Y10/00 ,  G11C13/02 ,  G11C2213/77 ,  G11C2213/81 ,  H03K19/02 ,  Y10S977/789

    摘要： Various embodiments of the present invention are directed to implementation and use of logic-state-storing, impedance-encoded nanoscale, impedance-encoded latches that store logic values as impedance states within nanoscale electronic circuits that employ impedance-driven logic. In certain of these embodiments, use of nanoscale, impedance-encoded latches together with nanoscale electronic circuits that employ impedance-driven logic avoids cumulative degradation of voltage margins along a cascaded series of logic circuits and provides for temporary storage of intermediate logic values, allowing for practical interconnection of nanowire-crossbar-implemented logic circuits through nanoscale, impedance-encoded latches to other nanowire-crossbar-implemented logic circuits in order to implement complex, nanoscale-logic-circuit pipelines, nanoscale-logic-circuit-based state machines, and other complex logic devices with various different interconnection topologies and corresponding functionalities.

    摘要翻译： 本发明的各种实施例涉及逻辑状态存储，阻抗编码的纳米级阻抗编码锁存器，其将逻辑值存储为采用阻抗驱动逻辑的纳米级电子电路内的阻抗状态。 在这些实施例的某些实施例中，使用纳米级阻抗编码的锁存器以及采用阻抗驱动逻辑的纳米级电子电路避免沿着级联的逻辑电路系列的电压裕度的累积劣化，并且提供中间逻辑值的临时存储，允许 将纳米线交叉开关逻辑电路通过纳米尺度阻抗编码的锁存器实际互连到其他纳米线交叉开关逻辑电路，以便实现复杂的纳米级逻辑电路管道，基于纳米级逻辑电路的状态机和 具有各种不同互连拓扑和相应功能的其他复杂逻辑器件。

    Autonomous evanescent optical nanosensor
    65.
    发明授权
    Autonomous evanescent optical nanosensor 失效
    自动渐逝光学纳米传感器

    公开(公告)号：US07233711B1

    公开(公告)日：2007-06-19

    申请号：US11127542

    申请日：2005-05-11

    申请人： Raymond G. Beausoleil ,  Philip J. Kuekes ,  R. Stanley Williams

    发明人： Raymond G. Beausoleil ,  Philip J. Kuekes ,  R. Stanley Williams

    IPC分类号： G02B6/00 ,  G02B6/12

    CPC分类号： G01N21/7703 ,  G01N21/648 ,  G01N21/65 ,  G01N21/94 ,  G01N33/569 ,  G01N35/00871 ,  G01N2021/7786 ,  G01N2035/00881

    摘要： A sensor includes traps that are adjacent to a waveguide and capable of holding a contaminant for an interaction with an evanescent field surrounding the waveguide. When held in a trap, a particle of the contaminant, which may be an atom, a molecule, a virus, or a microbe, scatters light from the waveguide, and the scattered light can be measured to detect the presence or concentration of the contaminant. Holding of the particles permits sensing of the contaminant in a gas where movement of the particles might otherwise be too fast to permit measurement of the interaction with the evanescent field. The waveguide, a lighting system for the waveguide, a photosensor, and a communications interface can all be fabricated on a semiconductor die to permit fabrication of an autonomous nanosensor capable of suspension in the air or a gas being sensed.

    摘要翻译： 传感器包括与波导相邻并且能​​够保持污染物以与与波导周围的ev逝场相互作用的陷阱。 当保持在陷阱中时，可能是原子，分子，病毒或微生物的污染物的颗粒散射来自波导的光，并且可以测量散射光以检测污染物的存在或浓度 。 保持颗粒允许感测气体中的污染物，其中颗粒的移动可能太快以至于不能测量与渐逝场的相互作用。 波导，用于波导的照明系统，光传感器和通信接口都可以在半导体管芯上制造，以允许制造能够在空气中悬浮的自主纳米传感器或被感测的气体。

    Demultiplexer for a molecular wire crossbar network (MWCN DEMUX)
    67.
    发明授权
    Demultiplexer for a molecular wire crossbar network (MWCN DEMUX) 有权
    分子线交叉网络解复用器（MWCN DEMUX）

    公开(公告)号：US06256767B1

    公开(公告)日：2001-07-03

    申请号：US09282049

    申请日：1999-03-29

    申请人： Philip J. Kuekes ,  R. Stanley Williams

    发明人： Philip J. Kuekes ,  R. Stanley Williams

    IPC分类号： G06F1750

    CPC分类号： G11C13/0009 ,  B82Y10/00 ,  G11C8/00 ,  G11C8/10 ,  G11C13/02 ,  G11C2213/14 ,  G11C2213/81 ,  Y10S977/943

    摘要： A demultiplexer for a two-dimensional array of a plurality of nanometer-scale switches (molecular wire crossbar network) is disclosed. Each switch comprises a pair of crossed wires which form a junction where one wire crosses another and at least one connector species connecting said pair of crossed wires in said junction. The connector species comprises a bi-stable molecule. The demultiplexer comprises a plurality of address lines accessed by a first set of wires in the two-dimensional array by randomly forming contacts between each wire in the first set of wires to at least one of the address lines. The first set of wires crosses a second set of wires to form the junctions. The demultiplexer solves both the problems of data input and output to a molecular electronic system and also bridges the size gap between CMOS and molecules with an architecture that can scale up to extraordinarily large numbers of molecular devices. Further, the demultiplexer is very defect tolerant, and can work despite a large number of defects in the system.

    摘要翻译： 公开了一种用于多个纳米级开关（分子线交叉网络）的二维阵列的解复用器。 每个开关包括一对交叉线，其形成一条线与另一条线交叉的连接处，以及连接所述连接处的所述一对交叉线的至少一个连接器种类。 连接器种类包括双稳态分子。 解复用器包括通过在第一组线中的每个线之间随机形成至少一个地址线的接触，由二维阵列中的第一组线路访问的多个地址线。 第一组导线穿过第二组电线以形成接合部。 解复用器解决了数据输入和输出到分子电子系统的问题，并且还利用可以扩展到非常大数量的分子器件的架构来桥接CMOS和分子之间的尺寸间隙。 此外，解复用器是非常缺陷容忍的，并且尽管系统中存在大量的缺陷，但它可以工作。

    Network connection scheme
    69.
    发明授权
    Network connection scheme 失效
    网络连接方案

    公开(公告)号：US5729752A

    公开(公告)日：1998-03-17

    申请号：US19499

    申请日：1993-02-19

    申请人： Gregory S. Snider ,  Philip J. Kuekes

    发明人： Gregory S. Snider ,  Philip J. Kuekes

    IPC分类号： G06F15/16 ,  G06F13/40 ,  G06F15/173 ,  H05K1/14 ,  G06F1/00

    CPC分类号： H05K1/14 ,  G06F13/409 ,  G06F15/17343

    摘要： A network connection scheme for a direct or an indirect network. The network is implemented in two levels of circuit boards. Every board in the first level crosses all the boards in the second level, with every processor in the first level circuit board coupled to at least two processors that are on two second level circuit boards. This scheme significantly reduces the difficulty in implementing the network.

    摘要翻译： 用于直接或间接网络的网络连接方案。 网络实现在两层电路板上。 第一级的每个电路板跨越第二级的所有电路板，第一级电路板中的每个处理器耦合到两个二级电路板上的至少两个处理器。 该方案大大降低了实现网络的难度。

    Crossbar switch connected modular multiprocessor system with processor timing relationship selected and synchronized to be appropriate for function being performed
    70.
    发明授权
    Crossbar switch connected modular multiprocessor system with processor timing relationship selected and synchronized to be appropriate for function being performed 失效
    交叉开关连接的模块化多处理器系统，选择和同步处理器时序关系，以适合正在执行的功能

    公开(公告)号：US5175824A

    公开(公告)日：1992-12-29

    申请号：US348544

    申请日：1989-05-08

    申请人： Robert W. Soderbery ,  Nicholas Dunckel ,  Philip J. Kuekes

    发明人： Robert W. Soderbery ,  Nicholas Dunckel ,  Philip J. Kuekes

    IPC分类号： G06F15/173

    CPC分类号： G06F15/17375

    摘要： This invention discloses a processing structure, and related method, for performing a selected data processing function by means of multiple processing modules that are selected to perform the selected function when appropriately connected together. The modules are removably connected to a common structure, such as a circuit board, which has associated with it a crossbar switch for providing intermodule data connections necessary for performing the selected function, and a synchronization unit for providing control signals to the modules to keep them in appropriate synchronism for performing the selected function. Convenient reconfiguration of the structure is effected by conditioning the crossbar switch and the synchronization unit as necessary to perform the different function.

    摘要翻译： 本发明公开了一种处理结构及相关方法，用于通过多个处理模块执行所选择的数据处理功能，所述多个处理模块被选择以在适当地连接在一起时执行所选择的功能。 模块可拆卸地连接到公共结构，例如电路板，其与其相关联，用于提供执行所选功能所需的模块间数据连接的交叉开关，以及用于向模块提供控制信号以保持它们的同步单元 用于执行所选功能的适当同步。 通过根据需要调节交叉开关和同步单元来实现结构的便利重新配置，以执行不同的功能。