公开(公告)号：US20220165937A1

公开(公告)日：2022-05-26

申请号：US17670842

申请日：2022-02-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jeffrey LILLE ,  Joyeeta NAG ,  Raghuveer S. MAKALA

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  G11C5/08

Abstract: A method of forming a magnetoresistive random access memory (MRAM) device includes providing a first die containing a selector material layer located over a first substrate, providing a second die containing a MRAM layer stack located over a second substrate, and bonding the first die to the second die.

公开(公告)号：US20220157966A1

公开(公告)日：2022-05-19

申请号：US17097841

申请日：2020-11-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bhagwati PRASAD ,  Joyeeta NAG ,  Seung-Yeul YANG ,  Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA

IPC: H01L29/51 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/78 ,  H01L21/28 ,  H01L21/3115 ,  H01L29/66

Abstract: A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.

公开(公告)号：US20220139960A1

公开(公告)日：2022-05-05

申请号：US17579183

申请日：2022-01-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Adarsh RAJASHEKHAR ,  Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA

IPC: H01L27/11597 ,  H01L27/1159

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of charge storage elements, a vertical semiconductor channel, a ferroelectric material layer located between the vertical stack of charge storage elements and the vertical semiconductor channel, and a blocking dielectric layer located between the ferroelectric material layer and the vertical semiconductor channel. A tunneling dielectric layer is located between at least one of the electrically conductive layers and the vertical stack of charge storage elements.

公开(公告)号：US20220059462A1

公开(公告)日：2022-02-24

申请号：US17000934

申请日：2020-08-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Yao-Sheng LEE

IPC: H01L23/535 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/532 ,  H01L21/02 ,  H01L21/768

Abstract: A semiconductor structure includes first metal lines located above at least one semiconductor device, and a continuous metal organic framework (MOF) material layer including lower MOF portions that are located between neighboring pairs of first metal lines and an upper MOF matrix portion that continuously extends over the first metal lines and connected to each of the lower MOF portions.

公开(公告)号：US20210408020A1

公开(公告)日：2021-12-30

申请号：US16913766

申请日：2020-06-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. MAKALA ,  Johann ALSMEIER

IPC: H01L27/11507 ,  H01L27/22 ,  H01L27/24 ,  H01L27/11504 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L45/00

Abstract: At least a portion of a memory cell is formed over a first substrate and at least a portion of a steering element or word or bit line of the memory cell is formed over a second substrate. The at least a portion of the memory cell is bonded to at least a portion of a steering element or word or bit line. At least one of the first or second substrate may be removed after the bonding.

公开(公告)号：US20210193585A1

公开(公告)日：2021-06-24

申请号：US16722824

申请日：2019-12-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Senaka KANAKAMEDALA ,  Fei ZHOU ,  Raghuveer S. MAKALA ,  Yao-Sheng LEE

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556

Abstract: A structure, such as a semiconductor device, includes metal line structures located over a substrate and laterally spaced apart from each other. Each of the metal line structures includes planar metallic liner including a first metal element and a metal line body portion includes a second metal element that is different from the first metal element. Metal-organic framework (MOF) material portions are located between neighboring pairs of the metal line structures and contain metal ions or clusters of the first metal element and organic ligands connected to the metal ions or clusters of the first metal element. Air gaps may be formed in the MOF material portions to further reduce the effective dielectric constant.

公开(公告)号：US20210050372A1

公开(公告)日：2021-02-18

申请号：US16743436

申请日：2020-01-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Yanli ZHANG ,  Seung-Yeul YANG ,  Fei ZHOU

IPC: H01L27/11597 ,  G11C11/22 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A ferroelectric memory device includes a semiconductor channel, a gate electrode, and a ferroelectric memory element located between the semiconductor channel and the gate electrode. The ferroelectric memory element includes at least one ferroelectric material portion and at least one antiferroelectric material portion.

公开(公告)号：US20210050371A1

公开(公告)日：2021-02-18

申请号：US16541289

申请日：2019-08-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Seung-Yeul YANG ,  Fei ZHOU ,  Adarsh RAJASHEKHAR

IPC: H01L27/11597 ,  G11C11/22 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11592

Abstract: A three-dimensional ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where each of the electrically conductive layers contains a respective transition metal nitride liner and a respective conductive fill material layer, a vertical semiconductor channel vertically extending through the alternating stack, a vertical stack of transition metal nitride spacers laterally surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers, and discrete ferroelectric material portions laterally surrounding the respective transition metal nitride spacers and located at the levels of the electrically conductive layers.

公开(公告)号：US20190287916A1

公开(公告)日：2019-09-19

申请号：US16020008

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Adarsh RAJASHEKHAR ,  Tatsuya HINOUE ,  Tomoyuki OBU ,  Tomohiro UNO ,  Yusuke MUKAE

IPC: H01L23/532 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768 ,  H01L29/49

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each of the electrically conductive layers includes a stack of a compositionally graded diffusion barrier and a metal fill material portion, and the compositionally graded diffusion barrier includes a substantially amorphous region contacting the interface between the compositionally graded diffusion barrier and a substantially crystalline region that is spaced from the interface by the amorphous region. The substantially crystalline region effectively blocks atomic diffusion, and the amorphous region induces formation of large grains during deposition of the metal fill material portions.

公开(公告)号：US20180374865A1

公开(公告)日：2018-12-27

申请号：US15632983

申请日：2017-06-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Seiji SHIMABUKURO ,  Raghuveer S. MAKALA

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66 ,  H01L23/535

CPC classification number: H01L27/11582 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/66553 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7849 ,  H01L29/7889 ,  H01L29/7926

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. A retro-stepped dielectric material portion comprising a compressive-stress-generating dielectric material on stepped surfaces of the alternating stack. Memory stack structures are formed through the first-tier alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a memory film. A patterned tensile-stress-generating material layer is formed over the retro-stepped dielectric material portion in a region that is laterally spaced outward from an outer periphery of a topmost layer within the alternating stack. The patterned tensile-stress-generating material layer applies a tensile stress to the retro-stepped dielectric material portion and to the alternating stack to compensate for the compressive stress generated by the retro-stepped dielectric material portion.