公开(公告)号：US10410722B2

公开(公告)日：2019-09-10

申请号：US15987207

申请日：2018-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Kim ,  Bong-Soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: H01L27/00 ,  G11C14/00 ,  H01L27/24 ,  H01L23/528 ,  H01L45/00 ,  G11C13/00 ,  G11C11/00 ,  G11C5/02 ,  H01L27/108

Abstract: A semiconductor device includes: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed on a substrate; and a second memory section and a wiring section that are stacked on the second peripheral circuit section, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, and the wiring section includes a plurality of line patterns, wherein the line patterns and the second memory cells are higher than the capacitor with respect to the substrate.

公开(公告)号：US20190206869A1

公开(公告)日：2019-07-04

申请号：US16115693

申请日：2018-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung Kim ,  Kiseok Lee ,  Junsoo Kim ,  Sunghee Han ,  Bong-Soo Kim ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L29/10 ,  H01L23/528 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate and a stack including a plurality of layers on the substrate. Each of the plurality of layers includes semiconductor patterns and a first conductive line that is connected to at least one of the semiconductor patterns. A second conductive line and a third conductive line penetrate the stack. The semiconductor patterns include a first semiconductor pattern and a second semiconductor pattern that are adjacent and spaced apart from each other in a first layer among the plurality of layers. The third conductive line is between, and connected in common to, the first and second semiconductor patterns.

公开(公告)号：US10211091B2

公开(公告)日：2019-02-19

申请号：US15334469

申请日：2016-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Dong Lee ,  Keunnam Kim ,  Dongryul Lee ,  Minseong Choi ,  Jimin Choi ,  Yong Kwan Kim ,  Changhyun Cho ,  Yoosang Hwang

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L27/108

Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

公开(公告)号：US20180286870A1

公开(公告)日：2018-10-04

申请号：US15845141

申请日：2017-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Semyeong Jang ,  Jemin Park ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L29/792 ,  H01L21/28 ,  H01L21/71

CPC classification number: H01L27/10885 ,  H01L21/28273 ,  H01L21/71 ,  H01L21/823475 ,  H01L27/10808 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10882 ,  H01L29/40114 ,  H01L29/7926

Abstract: A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.

公开(公告)号：US09985033B2

公开(公告)日：2018-05-29

申请号：US15397842

申请日：2017-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Kyung-Eun Kim ,  Bong-Soo Kim ,  Ki-hyung Nam ,  Yoosang Hwang

IPC: H01L23/48 ,  H01L27/108 ,  H01L29/423

CPC classification number: H01L27/10811 ,  H01L27/10814 ,  H01L27/10847 ,  H01L29/4238

Abstract: A semiconductor device including a capacitor is provided. The semiconductor device includes lower electrodes, each of which includes a first electrode and a second electrode stacked in a first direction. The second electrode has a pillar shape that has a bar-type cross section having a longitudinal axis when viewed from a cross-sectional view taken along a plane defined by second and third directions perpendicular to the first direction.

公开(公告)号：US09929013B2

公开(公告)日：2018-03-27

申请号：US15402545

申请日：2017-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Yoosang Hwang

IPC: H01L21/033 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L27/11531 ,  H01L27/11575

Abstract: Methods of fabricating a semiconductor device are provided. The methods may include etching a bulk pattern on a peripheral region to form patterns and then forming a layer on both a cell region and a peripheral region. The methods may include forming line patterns that extend from the cell region onto the peripheral region and then forming a layer on both the cell region and a peripheral region.

公开(公告)号：US20180040561A1

公开(公告)日：2018-02-08

申请号：US15782556

申请日：2017-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Hui-Jung Kim ,  Keunnam Kim ,  Daeik Kim ,  Bong-soo Kim ,  Yoosang Hwang

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L27/108 ,  H01L27/24

Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

公开(公告)号：US09871093B2

公开(公告)日：2018-01-16

申请号：US15383159

申请日：2016-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Kim ,  Ki-hyung Nam ,  Byung Yoon Kim ,  Bong-Soo Kim ,  Eunjung Kim ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L28/56 ,  H01L27/10808 ,  H01L27/10817 ,  H01L27/10847 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/82 ,  H01L28/88 ,  H01L28/90 ,  H01L28/92

Abstract: Provided is a semiconductor device. The semiconductor device includes a capacitor structure including a plurality of lower electrodes, a dielectric layer that covers surfaces of the plurality of lower electrodes, and an upper electrode on the dielectric layer. The semiconductor device further includes a support structure that supports the plurality of lower electrodes. The support structure includes a first support region that covers sidewalls of one of the plurality of lower electrodes, and an opening that envelops the first support region when the semiconductor device is viewed in plan view.

公开(公告)号：US20170200609A1

公开(公告)日：2017-07-13

申请号：US15402545

申请日：2017-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik KIM ,  Bong-Soo Kim ,  Jemin Park ,  Yoosang Hwang

IPC: H01L21/033 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L27/11531 ,  H01L27/11575

Abstract: Methods of fabricating a semiconductor device are provided. The methods may include etching a bulk pattern on a peripheral region to form patterns and then forming a layer on both a cell region and a peripheral region. The methods may include forming line patterns that extend from the cell region onto the peripheral region and then forming a layer on both the cell region and a peripheral region.

公开(公告)号：US09087728B2

公开(公告)日：2015-07-21

申请号：US14097937

申请日：2013-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Woo Chung ,  Jiyoung Kim ,  Yoosang Hwang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894

Abstract: A method of manufacturing a semiconductor device includes forming device isolation layer in a substrate to define active regions of which each has first regions and a second region between the first regions, forming a first trench and a pair of second trenches in the substrate, and forming gates in the second trenches, respectively. The first trench extends in a first direction and crosses the active regions and the device isolation layer. The second trenches are connected to a bottom of the first trench and extend in the first direction at both sides of the second regions.

Abstract translation: 一种制造半导体器件的方法包括在衬底中形成器件隔离层，以限定其中各具有第一区域的有源区和在第一区之间的第二区，在衬底中形成第一沟槽和一对第二沟槽， 分别在第二壕沟的大门。 第一沟槽沿第一方向延伸并与有源区和器件隔离层交叉。 第二沟槽连接到第一沟槽的底部并且在第二区域的两侧沿第一方向延伸。