公开(公告)号：US20200006328A1

公开(公告)日：2020-01-02

申请号：US16483302

申请日：2018-01-31

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Yuta ENDO ,  Shinya SASAGAWA ,  Shuhei NAGATSUKA

IPC: H01L27/07 ,  H01L29/786

Abstract: A favorable semiconductor device for miniaturization and high integration is provided. One embodiment of the present invention includes a first oxide including a first region and second region adjacent to each other, a third region and a fourth region with the first region and the second region provided therebetween, a second oxide over the first region, a first insulator over the second oxide, a first conductor over the first insulator, a second insulator over the second oxide and on side surfaces of the first insulator and the first conductor, a third insulator over the second region and on a side surface of the second insulator, and a second conductor over the second region with the third insulator provided therebetween. A part of the third insulator is positioned between the second conductor and the side surface of the second insulator.

公开(公告)号：US20190312149A1

公开(公告)日：2019-10-10

申请号：US16437642

申请日：2019-06-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Hiromi SAWAI ,  Hajime KIMURA

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/10 ,  H01L27/12 ,  H01L29/49

Abstract: A high-performance and highly reliable semiconductor device is provided. The semiconductor device includes: a first oxide; a source electrode; a drain electrode; a second oxide over the first oxide, the source electrode, and the drain electrode; a gate insulating film over the second oxide; and a gate electrode over the gate insulating film. The source electrode is electrically connected to the first oxide. The drain electrode is electrically connected to the first oxide. Each of the first oxide and the second oxide includes In, an element M (M is Al, Ga, Y, or Sn), and Zn. Each of the first oxide and the second oxide includes more In atoms than element M atoms. An atomic ratio of the In, the Zn, and the element M in the first oxide is equal to or similar to an atomic ratio of the In, the Zn, and the element M in the second oxide.

公开(公告)号：US20180331229A1

公开(公告)日：2018-11-15

申请号：US16030928

申请日：2018-07-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yuta ENDO ,  Yoko TSUKAMOTO

IPC: H01L29/786 ,  H01L29/423

CPC classification number: H01L29/7869 ,  H01L29/42392 ,  H01L29/78696

Abstract: To provide a miniaturized transistor having highly stable electrical characteristics. Furthermore, also in a semiconductor device including the transistor, high performance and high reliability are achieved. The transistor includes, over a substrate, a conductor, an oxide semiconductor, and an insulator. The oxide semiconductor includes a first region and a second region. The resistance of the second region is lower than that of the first region. The entire surface of the first region in the oxide semiconductor is surrounded in all directions by the conductor with the insulator interposed therebetween.

公开(公告)号：US20180248010A1

公开(公告)日：2018-08-30

申请号：US15903097

申请日：2018-02-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Hideomi SUZAWA ,  Kazuya HANAOKA ,  Shinya SASAGAWA ,  Satoru OKAMOTO

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  H01L29/49 ,  H01L29/423 ,  H01L27/146

CPC classification number: H01L29/78696 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1211 ,  H01L27/1225 ,  H01L27/1288 ,  H01L27/14616 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/66969 ,  H01L29/785 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78693 ,  H01L2029/42388

Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.

公开(公告)号：US20180061989A1

公开(公告)日：2018-03-01

申请号：US15685040

申请日：2017-08-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO

IPC: H01L29/786 ,  H01L29/10 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7869 ,  H01L21/823412 ,  H01L27/088 ,  H01L27/1225 ,  H01L29/1033 ,  H01L29/78648 ,  H01L29/78696

Abstract: A high-performance semiconductor device with high reliability is provided. The semiconductor device includes a first transistor, a second transistor, a first metal oxide covering at least part of the first transistor, an insulating film over the first transistor and the second transistor, and a second metal oxide over the insulating film. The first transistor includes a first gate electrode, a first gate insulating film, a first oxide, a first source electrode, a first drain electrode, a second gate insulating film, and a second gate electrode. The second transistor includes a third gate electrode, a third gate insulating film, a second oxide, a second source electrode, a second drain electrode, a fourth gate insulating film, and a fourth gate electrode. The first gate insulating film and the second gate insulating film are in contact with the first metal oxide.

公开(公告)号：US20170236839A1

公开(公告)日：2017-08-17

申请号：US15420628

申请日：2017-01-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yuta ENDO ,  Kiyoshi KATO ,  Satoru OKAMOTO

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/768 ,  H01L27/105 ,  H01L23/528 ,  H01L23/532 ,  H01L29/24 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L27/1207 ,  H01L21/0206 ,  H01L21/0214 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76834 ,  H01L21/8258 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869

Abstract: A highly reliable semiconductor device suitable for miniaturization and high integration is provided. The semiconductor device includes a first insulator; a transistor over the first insulator; a second insulator over the transistor; a first conductor embedded in an opening in the second insulator; a barrier layer over the first conductor; a third insulator over the second insulator and over the barrier layer; and a second conductor over the third insulator. The first insulator, the third insulator, and the barrier layer have a barrier property against oxygen and hydrogen. The second insulator includes an excess-oxygen region. The transistor includes an oxide semiconductor. The barrier layer, the third insulator, and the second conductor function as a capacitor.

公开(公告)号：US20170207347A1

公开(公告)日：2017-07-20

申请号：US15408719

申请日：2017-01-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Hideomi SUZAWA ,  Kazuya HANAOKA ,  Shinya SASAGAWA ,  Satoru OKAMOTO

IPC: H01L29/786 ,  H01L29/423 ,  H01L27/146 ,  H01L29/49 ,  H01L27/12 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/78696 ,  H01L27/1225 ,  H01L27/14616 ,  H01L29/401 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78693 ,  H01L2029/42388

Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.

公开(公告)号：US20160380106A1

公开(公告)日：2016-12-29

申请号：US15259294

申请日：2016-09-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Toshinari SASAKI ,  Kosei NODA ,  Mizuho SATO ,  Mitsuhiro ICHIJO ,  Toshiya ENDO

IPC: H01L29/786 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/7869 ,  H01L29/24 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78606

Abstract: In a transistor having a top-gate structure in which a gate electrode layer overlaps with an oxide semiconductor layer which faints a channel region with a gate insulating layer interposed therebetween, when a large amount of hydrogen is contained in the insulating layer, hydrogen is diffused into the oxide semiconductor layer because the insulating layer is in contact with the oxide semiconductor layer; thus, electric characteristics of the transistor are degraded. An object is to provide a semiconductor device having favorable electric characteristics. An insulating layer in which the concentration of hydrogen is less than 6×1020 atoms/cm3 is used for the insulating layer being in contact with oxide semiconductor layer which forms the channel region. Using the insulating layer, diffusion of hydrogen can be prevented and a semiconductor device having favorable electric characteristics can be provided.

公开(公告)号：US20160336454A1

公开(公告)日：2016-11-17

申请号：US15147279

申请日：2016-05-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78696

Abstract: A miniaturized transistor with less variation and highly stable electrical characteristics is provided. Further, high performance and high reliability of a semiconductor device including the transistor are achieved. A semiconductor and a conductor are formed over a substrate, a sacrificial layer is formed over the conductor, and an insulator is formed to cover the sacrificial layer. After that, a top surface of the insulator is removed to expose a top surface of the sacrificial layer. The sacrificial layer and a region of the conductor overlapping with the sacrificial layer are removed, whereby a source region, a drain region, and an opening are formed. Next, a gate insulator and a gate electrode are formed in the opening.

Abstract translation: 提供了具有较小变化和高度稳定的电特性的小型化晶体管。 此外，实现了包括晶体管的半导体器件的高性能和高可靠性。 半导体和导体形成在衬底上，牺牲层形成在导体上方，并且形成绝缘体以覆盖牺牲层。 之后，去除绝缘体的顶表面以暴露牺牲层的顶表面。 消除牺牲层和与牺牲层重叠的导体的区域，由此形成源极区域，漏极区域和开口。 接下来，在开口中形成栅极绝缘体和栅电极。

公开(公告)号：US20160247832A1

公开(公告)日：2016-08-25

申请号：US15041502

申请日：2016-02-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideomi SUZAWA ,  Yuta ENDO ,  Kazuya HANAOKA

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L21/475 ,  H01L21/47573 ,  H01L27/1207 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device with reduced parasitic capacitance is provided. The semiconductor device includes a first insulating layer; a first oxide layer over the first insulating layer; a semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer over the semiconductor layer; a second insulating layer over the first insulating layer; a third insulating layer over the second insulating layer, the source electrode layer, and the drain electrode layer; a second oxide layer over the semiconductor layer; a gate insulating layer over the second oxide layer; a gate electrode layer over the gate insulating layer; and a fourth insulating layer over the third insulating layer, the second oxide layer, the gate insulating layer, and the gate electrode layer.

Abstract translation: 提供具有降低的寄生电容的半导体器件。 半导体器件包括第一绝缘层; 第一绝缘层上的第一氧化物层; 在所述第一氧化物层上的半导体层; 半导体层上的源电极层和漏电极层; 在所述第一绝缘层上的第二绝缘层; 在第二绝缘层上的第三绝缘层，源电极层和漏电极层; 半导体层上的第二氧化物层; 第二氧化物层上的栅极绝缘层; 栅绝缘层上的栅电极层; 以及第三绝缘层，第二氧化物层，栅极绝缘层和栅极电极层上的第四绝缘层。