公开(公告)号：US06885072B1

公开(公告)日：2005-04-26

申请号：US10715931

申请日：2003-11-18

申请人： Erik S. Jeng

发明人： Erik S. Jeng

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/792 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28282 ,  H01L29/4232 ,  H01L29/7923

摘要： The present invention discloses a nonvolatile memory with undercut trapping structure, the nonvolatile memory comprising a semiconductor substrate. A gate oxide is formed on the semiconductor substrate. A gate structure is formed on the gate oxide, wherein the gate structure including a undercut structure formed at lower portion of the gate structure and inwardly into the gate structure. An isolation layer is formed over the sidewall of the gate structure. First spacers are formed on the sidewall of the isolation layer and filled into the undercut structure for storing carrier and source and drain regions formed adjacent to the gate structure and under the undercut structure. Salicide is formed on the gate structure and the source and drain regions.

摘要翻译： 本发明公开了一种具有底切捕获结构的非易失性存储器，所述非易失性存储器包括半导体衬底。 在半导体衬底上形成栅极氧化物。 栅极结构形成在栅极氧化物上，其中栅极结构包括形成在栅极结构的下部并且向内进入栅极结构的底切结构。 在栅极结构的侧壁上形成隔离层。 第一间隔物形成在隔离层的侧壁上，并被填充到底切结构中，用于储存形成在门结构附近和下切结构下的载流子和源区和漏区。 栅极结构和源极和漏极区域形成硅化物。

公开(公告)号：US06649475B1

公开(公告)日：2003-11-18

申请号：US10158154

申请日：2002-05-31

申请人： Wen-Ying Wen ,  Jyhlong Horng ,  Erik S. Jeng ,  Bai-Jun Kuo ,  Chih-Hsueh Hung

发明人： Wen-Ying Wen ,  Jyhlong Horng ,  Erik S. Jeng ,  Bai-Jun Kuo ,  Chih-Hsueh Hung

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7885

摘要： The structure of the FLASH device includes a first dielectric layer formed on a substrate. A floating gate with spacer profile formed on the first dielectric layer. A dielectric spacer is formed on the floating gate for isolation. A second dielectric layer is formed along the approximately vertical surface of the floating gate and the dielectric spacer and a lateral portion of the second dielectric layer laterally extends over the substrate adjacent the floating gate. A control gate is formed on the lateral portion of the second dielectric layer that laterally extends over the substrate. The control gate is formed on the lateral portion of the second dielectric layer.

摘要翻译： FLASH器件的结构包括形成在衬底上的第一介电层。 具有形成在第一电介质层上的间隔物轮廓的浮动栅极。 在浮动栅上形成介质隔离层用于隔离。 沿着浮动栅极和电介质间隔物的大致垂直表面形成第二电介质层，并且第二电介质层的横向部分在靠近浮动栅极的基板上横向延伸。 控制栅极形成在第二电介质层的横向延伸超过衬底的横向部分上。 控制栅极形成在第二介质层的侧面部分上。

公开(公告)号：US06248643B1

公开(公告)日：2001-06-19

申请号：US09285534

申请日：1999-04-02

申请人： Chien-Sheng Hsieh ,  Wei-Ray Lin ,  Fu-Liang Yang ,  Erik S. Jeng ,  Bor-Ru Sheu

发明人： Chien-Sheng Hsieh ,  Wei-Ray Lin ,  Fu-Liang Yang ,  Erik S. Jeng ,  Bor-Ru Sheu

IPC分类号： H01L2176

CPC分类号： H01L21/76897 ,  H01L21/32053 ,  H01L21/76224 ,  H01L21/76879 ,  H01L21/76885

摘要： A method for fabricating self-aligned contacts using elevated trench isolation, selective contact plug deposition and planarization starting at the device level. The process begins by successively forming a gate oxide layer and a first gate electrode layer on a silicon substrate. Next, fully planarized trench isolation regions are formed using sacrificial oxide and nitride layers and selective etching. A sacrificial pad oxide layer and a first sacrificial nitride layer are formed. The first sacrificial nitride layer, the sacrificial pad oxide layer, the first gate electrode layer, the gate oxide layer, and the silicon substrate are patterned to form trenches. A fill oxide layer is deposited in the trenches and over the first sacrificial nitride layer. An oxide etch is performed which recesses the fill oxide layer in the trenches below the level of the top of the first nitride layer. A second sacrificial nitride layer is formed on the fill oxide layer and over the first sacrificial nitride layer. Chemical-mechanical polishing is performed. Successive oxide etch, nitride etch and oxide etch steps are performed defining elevated trench isolation regions fully planarized with the first gate electrode layer. A silicide layer, a dielectric layer and a top nitride layer are formed. The top nitride layer, the dielectric layer, the silicide layer, the first gate electrode layer and the gate oxide layer are patterned forming gate structures between elevated trench isolation regions and conductive lines on elevated trench isolation regions. Spacers are formed on the sidewalls of the gate structures, the conductive lines and the elevated trench isolation regions. Then, self-aligned contact plugs are formed adjacent to the spacers.

摘要翻译： 一种使用升高的沟槽隔离，选择性接触插塞沉积和平面化从器件级开始制造自对准触点的方法。 该工艺开始于在硅衬底上依次形成栅氧化层和第一栅电极层。 接下来，使用牺牲氧化物和氮化物层和选择性蚀刻形成完全平坦化的沟槽隔离区域。 形成牺牲衬垫氧化物层和第一牺牲氮化物层。 图案化第一牺牲氮化物层，牺牲焊盘氧化物层，第一栅极电极层，栅极氧化物层和硅衬底以形成沟槽。 填充氧化物层沉积在沟槽中并在第一牺牲氮化物层上方。 执行氧化物蚀刻，其将沟槽中的填充氧化物层的凹陷低于第一氮化物层的顶部的水平面。 第二牺牲氮化物层形成在填充氧化物层上并在第一牺牲氮化物层上方。 进行化学机械抛光。 执行连续氧化物蚀刻，氮化物蚀刻和氧化物蚀刻步骤，定义与第一栅极电极层完全平坦化的升高的沟槽隔离区域。 形成硅化物层，电介质层和顶部氮化物层。 在顶部氮化物层，电介质层，硅化物层，第一栅极电极层和栅极氧化物层之间，在升高的沟槽隔离区域和升高的沟槽隔离区域上的导电线之间构图形成栅极结构。 隔板形成在栅极结构，导电线和升高的沟槽隔离区的侧壁上。 然后，在间隔物附近形成自对准的接触塞。

公开(公告)号：US06245656B1

公开(公告)日：2001-06-12

申请号：US09435512

申请日：1999-11-08

申请人： Bi-Ling Chen ,  Erik S. Jeng ,  Shih-Ming Chang

发明人： Bi-Ling Chen ,  Erik S. Jeng ,  Shih-Ming Chang

IPC分类号： H01L214763

CPC分类号： H01L21/76816 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  Y10S438/952

摘要： The present invention relates to a method for overcming problems of amplified exposure light interference from shrinked devices and difficulties of photolithographic and etching process control due to multi-level contacts. The present invention combines reflective lights from multiple levels into one single light and reduces interference of reflective lights by introducing a reflective coating and an anti-reflective coating of SiON/Ti or SiON/TiN/Ti which further serve as an etching hard mask for avoiding overetching. The process windows are expanded. Semiconductor devices can be further shrunk and production yields an be improved.

摘要翻译： 本发明涉及一种用于过滤来自收缩装置的放大的曝光光干涉的问题的方法以及由于多层接触导致的光刻和蚀刻工艺控制的困难。 本发明将来自多层的反射光组合成一个单一的光，并通过引入SiON / Ti或SiON / TiN / Ti的反射涂层和抗反射涂层来减少反射光的干扰，SiON / Ti或SiON / TiN / Ti进一步用作蚀刻硬掩模以避免 过蚀刻 进程窗口展开。 半导体器件可以进一步收缩并且产量得到改善。

公开(公告)号：US06180489B2

公开(公告)日：2001-01-30

申请号：US09290922

申请日：1999-04-12

申请人： Fu-Liang Yang ,  Bih-Tiao Lin ,  Wei-Ray Lin ,  Erik S. Jeng

发明人： Fu-Liang Yang ,  Bih-Tiao Lin ,  Wei-Ray Lin ,  Erik S. Jeng

IPC分类号： H01L2176

CPC分类号： H01L21/76229

摘要： A method for forming planarized shallow trench isolation is described. A nitride layer is deposited over the surface of a semiconductor substrate. A plurality of isolation trenches are etched through the nitride layer into the semiconductor substrate wherein there are at least one wide trench and at least one narrow trench. A first oxide layer is deposited over the first nitride layer and within the isolation trenches wherein the first oxide layer fills the isolation trenches. A capping nitride layer is deposited overlying the first oxide layer. A second oxide layer is deposited overlying the capping nitride layer. The second oxide layer is polished away wherein the second oxide layer and the capping nitride layer are left only within the wide trench. The first and second oxide layers are dry etched away with an etch stop on the capping nitride layer within the wide trench and the first nitride layer wherein the second oxide layer is completely removed. Thereafter, the first oxide layer is overetched to leave the top surface of the first oxide layer just above the bottom surface of the first nitride layer and the capping nitride layer within the wide trench. The capping nitride layer and the first nitride layer are removed completing the formation of shallow trench isolation regions in the fabrication of an integrated circuit device.

摘要翻译： 描述了形成平坦化浅沟槽隔离的方法。 在半导体衬底的表面上沉积氮化物层。 通过氮化物层将多个隔离沟槽蚀刻到半导体衬底中，其中存在至少一个宽沟槽和至少一个窄沟槽。 第一氧化物层沉积在第一氮化物层之上并且在隔离沟槽内，其中第一氧化物层填充隔离沟槽。 覆盖第一氧化物层的覆盖氮化物层被沉积。 覆盖覆盖氮化物层的第二氧化物层被沉积。 抛光第二氧化物层，其中第二氧化物层和覆盖氮化物层仅留在宽沟槽内。 第一氧化物层和第二氧化物层在宽沟槽内的覆盖氮化物层上的蚀刻停止层和第二氧化物层被完全去除的第一氮化物层被干蚀刻掉。 此后，将第一氧化物层过蚀刻，以将第一氧化物层的顶表面刚好在第一氮化物层的底表面和宽沟槽内的覆盖氮化物层的上方。 在制造集成电路器件时，去除覆盖氮化物层和第一氮化物层，从而形成浅沟槽隔离区。

公开(公告)号：US6159839A

公开(公告)日：2000-12-12

申请号：US247977

申请日：1999-02-11

申请人： Erik S. Jeng ,  Bi-Ling Chen ,  Chien-Sheng Hsieh

发明人： Erik S. Jeng ,  Bi-Ling Chen ,  Chien-Sheng Hsieh

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/4763

CPC分类号： H01L27/10855 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10888 ,  H01L27/10894

摘要： A method for making a novel structure having borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections on integrated circuits is achieved. An etch-stop layer and a planar insulating layer are formed over the devices on a substrate. Contact openings are etched in the insulating layer to the etch-stop layer and the etch-stop layer is removed over the N.sup.- contact areas. An N.sup.+ doped polysilicon layer is deposited, and second contact openings are etched in the polysilicon and insulating layers over N.sup.+ and P.sup.+ contacts on the substrate to the etch-stop layer. The etch-stop layer is selectively removed and a conducting barrier layer and a metal layer are deposited having a second etch-stop layer on the surface. The layers are patterned to form interconnecting lines and concurrently to form polysilicon landing plugs to the N.sup.- contacts, while forming metal landing plugs to the N.sup.+ and P.sup.+ contacts. Via holes can now be etched in a second insulating layer over and to the landing plugs. The polysilicon landing plugs to the N.sup.- contacts reduce current leakage, while the metal contacts to the N.sup.+ and P.sup.+ contacts reduce the contact resistance (Rc). The landing plugs protect the substrate contacts from damage during via hole etch and reduce the aspect ratio for making more reliable contacts.

公开(公告)号：US6150213A

公开(公告)日：2000-11-21

申请号：US111685

申请日：1998-07-08

申请人： Hung-Yi Luo ,  Erik S. Jeng ,  Yue-Feng Chen

发明人： Hung-Yi Luo ,  Erik S. Jeng ,  Yue-Feng Chen

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L28/91 ,  H01L27/10873

摘要： The present invention includes forming polysilicon plugs between the gate structures and word lines in a BPSG layer formed on the gate structures and the word lines. A polysilicon layer, a tungsten silicide layer and a silicon oxide layer are sequentially formed on the BPSG layer. Then, the multi-layers are etched to the surface of the BPSG layer. Next, the BPSG layer is slightly etched to expose the polysilicon plug. Oxide spacers are formed on the sidewalls of the layers. A silicon nitride layer is formed over the bit lines, oxide spacers and on the polysilicon plugs. An oxide layer is formed on the silicon nitride layer. Subsequently, the oxide layer is patterned to form node contact holes. An etching is used to etch the silicon nitride layer. A first conductive layer is formed along the surface of the oxide layer, the contact holes. The top portion of the first conductive layer is removed. The oxide layer is removed to expose the silicon nitride layer. A dielectric film is deposited along the surface of the first conductive layer. Finally, a second conductive layer is formed over the dielectric film.

摘要翻译： 本发明包括在形成在栅极结构和字线上的BPSG层中的栅极结构和字线之间形成多晶硅插塞。 在BPSG层上依次形成多晶硅层，硅化钨层和氧化硅层。 然后，将多层蚀刻到BPSG层的表面。 接下来，稍微蚀刻BPSG层以暴露多晶硅插塞。 在层的侧壁上形成氧化物间隔物。 在位线，氧化物间隔物和多晶硅插塞上形成氮化硅层。 在氮化硅层上形成氧化物层。 随后，对氧化层进行图案化以形成节点接触孔。 蚀刻用于蚀刻氮化硅层。 沿着氧化物层的表面，接触孔形成第一导电层。 去除第一导电层的顶部。 去除氧化物层以露出氮化硅层。 沿着第一导电层的表面沉积电介质膜。 最后，在电介质膜上形成第二导电层。

公开(公告)号：US6074952A

公开(公告)日：2000-06-13

申请号：US74341

申请日：1998-05-07

申请人： Hao-Chieh Liu ,  Erik S. Jeng ,  Bi-Ling Chen ,  Wan-Yih Lien

发明人： Hao-Chieh Liu ,  Erik S. Jeng ,  Bi-Ling Chen ,  Wan-Yih Lien

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/306

CPC分类号： H01L27/10894 ,  H01L21/31116 ,  H01L21/76816 ,  H01L27/10882

摘要： A method of forming a plurality of contact holes 70 in a semiconductor wafer uses a single step. The semiconductor wafer includes a dielectric layer 69 overlying a silicon substrate 51, a silicon nitride layer 67a, and a silicon oxynitride layer 63c. First, a photoresist 68 layer is developed on the dielectric layer. Prior to forming the dielectric layer, the silicon oxynitride layer is formed overlying a first conductive layer, and the silicon nitride layer is formed overlying a second conductive layer. Second, an etching step is performed to etch through the silicon oxynitride layer, the silicon nitride layer, a portion of the dielectric layer above the silicon oxynitride layer, and the silicon nitride layer to expose the silicon substrate 51, the first conductive layer 63a, and the second conductive layer 67c. The etching recipe includes a first chemistry and a second chemistry. The first chemistry includes C.sub.2 F.sub.6, C.sub.4 F.sub.8, CH.sub.3 F, and Ar. The second chemistry is chosen from a group including O.sub.2, CO.sub.2, CO and any combination thereof. Thus, a plurality of contact holes is formed above the silicon substrate, the first conductive layer and the second conductive layer.

摘要翻译： 在半导体晶片中形成多个接触孔70的方法使用一个步骤。 半导体晶片包括覆盖硅衬底51的电介质层69，氮化硅层67a和氮氧化硅层63c。 首先，在电介质层上显影光致抗蚀剂68层。 在形成电介质层之前，形成氮氧化硅层，覆盖第一导电层，并且氮化硅层形成在第二导电层上。 其次，进行蚀刻步骤以蚀刻穿过氧氮化硅层，氮化硅层，氧氮化硅层上方的电介质层的一部分和氮化硅层，以暴露硅衬底51，第一导电层63a， 和第二导电层67c。 该蚀刻配方包括第一化学和第二化学。 第一种化学性质包括C2F6，C4F8，CH3F和Ar。 第二化学选自包括O 2，CO 2，CO及其任何组合的组。 因此，在硅衬底，第一导电层和第二导电层上形成多个接触孔。

公开(公告)号：US6037211A

公开(公告)日：2000-03-14

申请号：US841836

申请日：1997-05-05

申请人： Erik S. Jeng ,  Yue-Feng Chen ,  Bi-Ling Chen

发明人： Erik S. Jeng ,  Yue-Feng Chen ,  Bi-Ling Chen

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/28 ,  H01L21/336

CPC分类号： H01L27/10844 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897

摘要： A method of fabricating contact holes in high density integrated circuits uses landing plugs to reduce the aspect ratio of the the node contact holes in order to improve the processing window of deep contact holes. Along with nitride spacers on the sidewalls of a transistor gate structure, polysilicon hard masks and polysilicon spacers are used as etching masks in a self-aligned contact process. In addition, the landing plugs incorporate the polysilicon spacers as part of landing plug to increase the contact area. As a result, wide contact processing windows can be achieved in high density integrated circuits.

摘要翻译： 在高密度集成电路中制造接触孔的方法使用着陆塞以减小节点接触孔的纵横比，以改善深接触孔的加工窗口。 随着在晶体管栅极结构的侧壁上的氮化物间隔物，多晶硅硬掩模和多晶硅间隔物用作自对准接触工艺中的蚀刻掩模。 此外，着陆塞将多晶硅间隔件作为着陆塞的一部分，以增加接触面积。 因此，可以在高密度集成电路中实现广泛的接触处理窗口。

公开(公告)号：US6033962A

公开(公告)日：2000-03-07

申请号：US121692

申请日：1998-07-24

申请人： Erik S. Jeng ,  Hung-Yi Luo ,  Yue-Feng Chen ,  Ming-Horn Tsai

发明人： Erik S. Jeng ,  Hung-Yi Luo ,  Yue-Feng Chen ,  Ming-Horn Tsai

IPC分类号： H01L21/60 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/76897

摘要： A method for forming a self-aligned contact, (SAC), opening, for a semiconductor device, has been developed. The process features the formation of partial silicon nitride spacers, on the sides of polycide gate structures, via a partial anisotropic RIE procedure, applied to a silicon nitride layer, also resulting in a thin layer of silicon nitride remaining on regions between polycide gate structures. After deposition of an overlying insulator layer, a two step, anisotropic RIE procedure is used to create the SAC opening in the insulator layer, and in the underlying, thin silicon nitride layer. The first step, of the two step, SAC opening procedure, selectively removes first insulator layer, while the second step, of the two step, SAC opening procedure, selectively removes the thin silicon nitride layer.

摘要翻译： 已经开发了用于形成用于半导体器件的自对准接触（SAC），开口的方法。 该方法的特征在于在多晶硅栅极结构的侧面上经由施加到氮化硅层的部分各向异性RIE程序形成部分氮化硅间隔物，同时也导致在多晶硅栅极结构之间的区域上留下薄层的氮化硅。 在沉积上覆绝缘体层之后，使用两步各向异性RIE程序来在绝缘体层中以及在下面的薄氮化硅层中形成SAC开口。 第一步，两步骤，SAC打开程序，选择性地去除第一绝缘体层，而第二步，两步，SAC打开程序，选择性地去除薄氮化硅层。