公开(公告)号：US07732922B2

公开(公告)日：2010-06-08

申请号：US11970149

申请日：2008-01-07

申请人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

发明人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

IPC分类号： H01L29/40

CPC分类号： H01L23/53238 ,  H01L23/5226 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention is directed to an improved semiconductor structure, such that within the same insulating layer, Cu interconnects embedded within the same insulating level layer have a different Cu grain size than other Cu interconnects embedded within the same insulating level layer.

摘要翻译： 本发明涉及一种改进的半导体结构，使得在同一绝缘层内嵌入相同绝缘层的Cu互连件具有与嵌入在同一绝缘层中的其它Cu互连不同的Cu晶粒尺寸。

公开(公告)号：US07732322B2

公开(公告)日：2010-06-08

申请号：US11360350

申请日：2006-02-23

申请人： Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  Chih-Chao Yang

发明人： Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/31695 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/31633 ,  H01L21/7682 ,  H01L21/76831

摘要： In a first aspect, a first method of manufacturing a dielectric material with a reduced dielectric constant is provided. The first method includes the steps of (1) forming a dielectric material layer including a trench on a substrate; and (2) forming a cladding region in the dielectric material layer by forming a plurality of air gaps in the dielectric material layer along at least one of a sidewall and a bottom of the trench so as to reduce an effective dielectric constant of the dielectric material. Numerous other aspects are provided.

摘要翻译： 在第一方面，提供了制造介电常数降低的介电材料的第一种方法。 第一种方法包括以下步骤：（1）在衬底上形成包括沟槽的电介质材料层; 以及（2）通过沿着沟槽的侧壁和底部中的至少一个形成电介质材料层中的多个气隙，从而在电介质材料层中形成包层区域，从而降低电介质材料的有效介电常数 。 提供了许多其他方面。

公开(公告)号：US07727890B2

公开(公告)日：2010-06-01

申请号：US11953359

申请日：2007-12-10

申请人： Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S. Yang

发明人： Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S. Yang

IPC分类号： H01L21/44

CPC分类号： C25D5/02 ,  Y10T428/24331 ,  Y10T428/24917

摘要： Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed are embodiments of a method of forming such an electroplated metal structure by lining a high aspect ratio opening (e.g., a high aspect ratio via or trench) with a metal-plating seed layer and, then, forming a protective layer over the portion of the metal-plating seed layer adjacent to the opening sidewalls so that subsequent electroplating occurs only from the bottom surface of the opening up.

摘要翻译： 公开了改进的高宽比电镀金属结构（例如，铜或铜合金互连，例如线的后端（BEOL）或线的中间（MOL）接触）的实施例，其中电镀金属填充材料 没有接缝和/或空隙。 此外，公开了通过用金属电镀种子层衬里高纵横比开口（例如，高纵横比通孔或沟槽）形成这种电镀金属结构的方法的实施例，然后在其上形成保护层 金属电镀种子层的一部分与开口侧壁相邻，使得随后的电镀仅从开口的底表面发生。

公开(公告)号：US07692439B2

公开(公告)日：2010-04-06

申请号：US12154304

申请日：2008-05-22

申请人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

IPC分类号： G01R31/02 ,  H01L23/58 ,  G01N25/20

CPC分类号： G01R31/2858 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.

摘要翻译： 提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平 延伸平面 该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。 下导电或半导体元件可以与下通孔的底端接触。 上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。 上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。 该结构还可以包括与上金属通孔的顶端接触的上金属线元件。

公开(公告)号：US07670943B2

公开(公告)日：2010-03-02

申请号：US12179054

申请日：2008-07-24

申请人： Chih-Chao Yang ,  Griselda Bonilla ,  Shyng-Tsong Chen ,  Kelly Malone

发明人： Chih-Chao Yang ,  Griselda Bonilla ,  Shyng-Tsong Chen ,  Kelly Malone

IPC分类号： H01L21/4763

CPC分类号： H01L23/5226 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76877 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of the via located within the interlayer dielectric layer.

摘要翻译： 本发明提供了一种改进的可靠性的互连结构。 本发明的互连结构具有增强的由嵌入式金属衬垫提供的通孔触点的机械强度。 嵌入的金属衬垫可以是连续的或不连续的。 不连续的嵌入式金属衬垫由位于层间介质层内的通孔底部的不连续界面提供。

公开(公告)号：US07666787B2

公开(公告)日：2010-02-23

申请号：US11307761

申请日：2006-02-21

申请人： Chih-Chao Yang ,  Shom Ponoth

发明人： Chih-Chao Yang ,  Shom Ponoth

IPC分类号： H01L21/20

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the electromigration problem that is exhibited by prior art interconnect structures, are provided. In accordance with the present invention, a grain growth promotion layer, which promotes the formation of a conductive region within the interconnect structure that has a bamboo microstructure and an average grain size of larger than 0.05 microns is utilized. The inventive structure has improved performance and reliability.

摘要翻译： 提供了单镶嵌型或双镶嵌型的互连结构及其形成方法，其基本上减少了现有技术互连结构所呈现的电迁移问题。 根据本发明，利用促进在互连结构内形成具有竹微结构并且平均晶粒尺寸大于0.05微米的导电区域的晶粒生长促进层。 本发明的结构具有改进的性能和可靠性。

公开(公告)号：US07657995B2

公开(公告)日：2010-02-09

申请号：US11776835

申请日：2007-07-12

申请人： Louis Hsu ,  Timothy Dalton ,  Lawrence Clevenger ,  Carl Radens ,  Kwong Hon Wong ,  Chih-Chao Yang

发明人： Louis Hsu ,  Timothy Dalton ,  Lawrence Clevenger ,  Carl Radens ,  Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01H11/00 ,  H01H65/00

CPC分类号： H01H59/0009 ,  H01H1/20 ,  H01H2001/0084 ,  H01H2001/0089 ,  Y10T29/49105 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49208

摘要： A method of fabricating a MEMS switch that is fully integratable in a semiconductor fabrication line. The method consists of forming two posts, each end thereof terminating in a cap; a rigid movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; forming upper and lower electrode pairs and upper and lower interconnect wiring lines connected and disconnected by the rigid movable conductive plate. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines.

摘要翻译： 一种制造可在半导体制造生产线中完全集成的MEMS开关的方法。 该方法包括形成两个柱，其每端终止于盖中; 刚性可移动导电板，其表面终止于两个相对边缘中的每一个中的环中，所述环松散地连接到引导柱; 形成上下电极对以及由刚性可移动导电板连接和断开的上下互连布线。 导电板向上移动，使两条上部互连线路短路。 相反，当电压施加到下电极对时，导电板向下移动，而上电极对接地，使两个下互连布线短路并打开上布线。

公开(公告)号：US07651892B2

公开(公告)日：2010-01-26

申请号：US11535833

申请日：2006-09-27

申请人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  James J. Demarest ,  Louis C. Hsu ,  Carl Radens

发明人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  James J. Demarest ,  Louis C. Hsu ,  Carl Radens

IPC分类号： H01L21/20 ,  H01L21/82 ,  H01L21/44

CPC分类号： H01L23/5228 ,  H01L23/5256 ,  H01L23/5329 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides an electrical programmable metal resistor and a method of fabricating the same in which electromigration stress is used to create voids in the structure that increase the electrical resistance of the resistor. Specifically, a semiconductor structure is provided that includes an interconnect structure comprising at least one dielectric layer, wherein said at least one dielectric layer comprises at least two conductive regions and an overlying interconnect region embedded therein, said at least two conductive regions are in contact with said overlying interconnect region by at least two contacts and at least said interconnect region is separated from said at least one dielectric layer by a diffusion barrier, wherein voids are present in at least the interconnect region which increase the electrical resistance of the interconnect region.

摘要翻译： 本发明提供一种电可编程金属电阻器及其制造方法，其中电迁移应力用于在结构中产生增加电阻器的电阻的空隙。 具体而言，提供一种半导体结构，其包括包括至少一个电介质层的互连结构，其中所述至少一个电介质层包括至少两个导电区域和嵌入其中的覆盖互连区域，所述至少两个导电区域与 所述覆盖互连区域由至少两个触点和至少所述互连区域通过扩散阻挡层与所述至少一个介电层分离，其中空隙存在于至少互连区域中，这增加了互连区域的电阻。

公开(公告)号：US20090298281A1

公开(公告)日：2009-12-03

申请号：US12539488

申请日：2009-08-11

申请人： Chih-Chao Yang ,  Satya V. Nitta

发明人： Chih-Chao Yang ,  Satya V. Nitta

IPC分类号： H01L21/768

CPC分类号： H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure is provided in which the conductive feature (i.e., conductive material) is not coplanar with the upper surface of the dielectric material, but instead the conductive material is recessed below an upper surface of the dielectric material. In addition to being recessed below the upper surface of the dielectric material, the conductive material of the interconnect structure is surrounded on all sides (i.e., sidewall surfaces, upper surface and bottom surface) by a diffusion barrier material. Unlike prior art interconnect structures, the barrier material located on the upper surface of the recessed conductive material is located with an opening including the recessed conductive material.

摘要翻译： 提供了互连结构，其中导电特征（即，导电材料）不与电介质材料的上表面共面，而是导电材料凹陷在电介质材料的上表面下方。 除了凹陷在介电材料的上表面之外，互连结构的导电材料通过扩散阻挡材料在所有侧面（即，侧壁表面，上表面和底表面）上被包围。 与现有技术的互连结构不同，位于凹陷导电材料的上表面上的阻挡材料定位成具有包括凹入的导电材料的开口。

公开(公告)号：US20090297759A1

公开(公告)日：2009-12-03

申请号：US12127878

申请日：2008-05-28

申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Charles C. Goldsmith ,  Ping-Chuan Wang ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Charles C. Goldsmith ,  Ping-Chuan Wang ,  Chih-Chao Yang

IPC分类号： B05D5/12 ,  B32B3/02

CPC分类号： H01L21/76877 ,  H01L21/76883

摘要： Recrystallization and grain growth of metal, such as Cu, is achieved at higher anneal temperatures of 150° C. to 400° C., for example, for short anneal times of five to sixty minutes by forming a metal stress locking layer on the Cu before anneal and chemical-mechanical polishing. The stress locking layer extends the elastic region of the Cu by suppressing atom diffusion to the free surface, resulting in near zero tensile stress at room temperature after anneal. Stress voiding, which creates reliability problems, is thereby avoided. Improved grain size and texture are also achieved. The stress locking layer is removed after anneal by chemical-mechanical polishing leaving the Cu interconnect with low stress and improved grain size and texture.

摘要翻译： 在150℃至400℃的较高退火温度下实现诸如Cu的金属的重结晶和晶粒生长，例如，通过在Cu上形成金属应力锁定层，例如在短至五至六十分钟的短退火时间 在退火和化学机械抛光之前。 应力锁定层通过将原子扩散抑制到自由表面而延伸Cu的弹性区域，导致退火后在室温下拉伸应力接近零。 从而避免了造成可靠性问题的应力消除。 也实现了改善的晶粒尺寸和纹理。 通过化学机械抛光退火后去除应力锁定层，使Cu互连具有低应力和改善的晶粒尺寸和纹理。