公开(公告)号：US07732328B2

公开(公告)日：2010-06-08

申请号：US11866942

申请日：2007-10-03

申请人： Yong-Chai Kwon ,  Dong-Ho Lee

发明人： Yong-Chai Kwon ,  Dong-Ho Lee

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L23/5258 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05569 ,  H01L2224/13008 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A semiconductor package structure and a method of fabricating the same are disclosed. A method of fabricating the semiconductor package structure can be characterized as including forming semiconductor chips on a semiconductor substrate. Each of the semiconductor chips includes chip pads. Through-vias are formed through the semiconductor chips. Redistribution structures and a chip selection interconnection layer are formed on the semiconductor chips, which connect the through-vias with the chip pads. The chip selection interconnection layers are patterned to form chip selection interconnection lines having different structures on at least one of the semiconductor chips. The semiconductor chips are stacked and electrically connected using the through-vias.

摘要翻译： 公开了一种半导体封装结构及其制造方法。 制造半导体封装结构的方法可以表征为包括在半导体衬底上形成半导体芯片。 每个半导体芯片包括芯片焊盘。 通孔通过半导体芯片形成。 重新分配结构和芯片选择互连层形成在将通孔与芯片焊盘连接的半导体芯片上。 芯片选择互连层被图案化以在至少一个半导体芯片上形成具有不同结构的芯片选择互连线。 半导体芯片使用贯通孔堆叠并电连接。

公开(公告)号：US07644936B2

公开(公告)日：2010-01-12

申请号：US11606466

申请日：2006-11-29

申请人： Dong-Ho Lee

发明人： Dong-Ho Lee

IPC分类号： B60G3/26

CPC分类号： B62D17/00 ,  B60G7/006 ,  B60G2200/10 ,  B60G2200/464 ,  B60G2202/413 ,  B60G2204/148 ,  B60G2204/416 ,  B60G2204/4232 ,  B60G2204/62 ,  B60G2600/182 ,  B60G2800/24

摘要： Disclosed is a caster control apparatus for a suspension of a vehicle. When the vehicle travels on a road which causes a vehicle body to lean to one side, the caster of a lowered wheel is increased, and the caster of a raised wheel is decreased, such that the casters of the wheels on both sides are offset with each other. Therefore, the vehicle is inhibited from leaning due to the lateral slope of the road, and the straight-line stability of the vehicle can be reliably maintained.

摘要翻译： 公开了一种用于车辆悬架的脚轮控制装置。 当车辆在导致车体倾斜到一侧的道路上行驶时，下轮的脚轮增加，并且升轮的脚轮减小，使得两侧的车轮的脚轮偏移 彼此。 因此，由于道路的横向倾斜，车辆被阻止倾斜，能够可靠地保持车辆的直线稳定性。

公开(公告)号：US20090284423A1

公开(公告)日：2009-11-19

申请号：US12465416

申请日：2009-05-13

申请人： Kyung-Hack YI ,  Dong-Ho Lee

发明人： Kyung-Hack YI ,  Dong-Ho Lee

IPC分类号： H01Q1/24 ,  H01Q1/38

CPC分类号： H01Q1/2283 ,  H01Q1/243 ,  H01Q1/38 ,  H01Q7/08

摘要： A portable terminal with an antenna for receiving broadcast signals, includes an antenna module having a chip antenna patterned on a dielectric chip so as to define a physical length of the antenna module that enables the chip antenna to operate within a broadcast band, and a conductive plate connected to the chip antenna and having an area such that conductive plate leads a main radiation of the antenna module on the broadcast band, whereby the physical length of the antenna module can be reduced as short as possible by employing the chip antenna. Accordingly, the chip antenna facilitates making the antenna module and the portable terminal be smaller in size. Also, the chip antenna is configured to lead a main radiation on the conductive plate, thereby increasing radio reception quality and improving radio performance.

摘要翻译： 具有用于接收广播信号的天线的便携式终端包括天线模块，其具有图案化在介质芯片上的芯片天线，以便限定天线模块的物理长度，使得芯片天线能够在广播频带内工作，并且导电 连接到芯片天线的板，并且具有使得导电板在广播频带上引导天线模块的主辐射的区域，由此可以通过采用芯片天线尽可能地减小天线模块的物理长度。 因此，芯片天线有助于使天线模块和便携式终端的尺寸更小。 此外，芯片天线被配置为引导导电板上的主辐射，从而增加无线电接收质量并提高无线电性能。

公开(公告)号：US07602047B2

公开(公告)日：2009-10-13

申请号：US11979562

申请日：2007-11-06

申请人： Yong-Chai Kwon ,  Dong-Ho Lee ,  In-Young Lee

发明人： Yong-Chai Kwon ,  Dong-Ho Lee ,  In-Young Lee

IPC分类号： H01L29/40

CPC分类号： H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A method of fabricating a semiconductor device is provided. The method may include forming an insulating layer on a wafer. The wafer may have an active surface and an inactive surface which face each other, and the insulating layer may be formed on the active surface. A pad may be formed on the insulating layer, and a first hole may be formed in the insulating layer. A first hole insulating layer may then be formed on an inner wall of the first hole. A second hole may be formed under the first hole. The second hole may be formed to extend from the first hole into the wafer. A second hole insulating layer may be formed on an inner wall of the second hole. The semiconductor device fabricated according to the method may also be provided.

摘要翻译： 提供一种制造半导体器件的方法。 该方法可以包括在晶片上形成绝缘层。 晶片可以具有彼此面对的有源表面和非活性表面，并且绝缘层可以形成在有源表面上。 可以在绝缘层上形成焊盘，并且可以在绝缘层中形成第一孔。 然后可以在第一孔的内壁上形成第一孔绝缘层。 可以在第一孔下方形成第二孔。 第二孔可以形成为从第一孔延伸到晶片。 第二孔绝缘层可以形成在第二孔的内壁上。 还可以提供根据该方法制造的半导体器件。

公开(公告)号：US07588964B2

公开(公告)日：2009-09-15

申请号：US11790173

申请日：2007-04-24

申请人： Yong-Chai Kwon ,  Dong-Ho Lee ,  Myung-Kee Chung ,  Kang-Wook Lee ,  Sun-Won Kang ,  Keum-Hee Ma

发明人： Yong-Chai Kwon ,  Dong-Ho Lee ,  Myung-Kee Chung ,  Kang-Wook Lee ,  Sun-Won Kang ,  Keum-Hee Ma

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/12 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/90 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/83856 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： A stacked structure of semiconductor devices may include a plurality of stacked semiconductor devices, each having an upper surface and a lower surface and one or more via electrodes protruding from the upper surface to the lower surface. The via-electrodes may have upper parts (heads) protruding from the upper surface and lower parts (ends) protruding from the lower surface. The stacked semiconductor devices may be electrically connected to each other through the via-electrodes. A first adhesive film (e.g., patternable material) and a second adhesive film (e.g. puncturable material) may be formed between the stacked semiconductor devices. The stacked structure of semiconductor devices may be mounted on the upper surface of a printed circuit board (PCB) having a mount-specific adhesive film to form a semiconductor device package. The mounted stacked structure and the upper surface of the PCB may be further covered with a molding material.

摘要翻译： 半导体器件的层叠结构可以包括多个层叠的半导体器件，每个具有上表面和下表面以及从上表面到下表面突出的一个或多个通孔电极。 通孔电极可以具有从上表面突出的上部（头）和从下表面突出的下部（端部）。 层叠的半导体器件可以通过通孔电极彼此电连接。 可以在层叠的半导体器件之间形成第一粘合膜（例如，可图案化材料）和第二粘合膜（例如可刺穿材料）。 半导体器件的堆叠结构可以安装在具有安装专用粘合剂膜的印刷电路板（PCB）的上表面上以形成半导体器件封装。 安装的堆叠结构和PCB的上表面可以进一步被模制材料覆盖。

公开(公告)号：US07479408B2

公开(公告)日：2009-01-20

申请号：US11536611

申请日：2006-09-28

申请人： Dong-Ho Lee

发明人： Dong-Ho Lee

IPC分类号： H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/02

CPC分类号： H01L25/105 ,  H01L2224/4824 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/15311

摘要： A stack package of the present invention is made by stacking at least two area array type chip scale packages. Each chip scale package of an adjacent pair of chip scale packages is attached to the other in a manner that the ball land pads of the upper stacked chip scale package face in the opposite direction to those of the lower stacked chip scale package, and the circuit patterns of the upper stacked chip scale package are electrically connected to the those of the lower stacked chip scale package by, for example, connecting boards. Therefore, it is possible to stack not only fan-out type chip scale packages, but to also efficiently stack ordinary area array type chip scale packages.

摘要翻译： 通过堆叠至少两个区域阵列型芯片级封装件来制造本发明的堆叠封装。 相邻的一对芯片级封装的每个芯片级封装以上堆叠芯片级封装的焊盘焊盘与下堆叠芯片尺寸封装的方向相反的方式附接到另一芯片尺寸封装，并且电路 上堆叠芯片级封装的图案通过例如连接板电连接到下堆叠芯片级封装的图案。 因此，不仅可以堆叠扇出式芯片级封装，而且可以有效地堆叠普通区域阵列型芯片级封装。

公开(公告)号：US07450097B2

公开(公告)日：2008-11-11

申请号：US11144503

申请日：2005-06-03

申请人： Keun-Shik Nah ,  Dong-Ho Lee

发明人： Keun-Shik Nah ,  Dong-Ho Lee

IPC分类号： G09G3/36

CPC分类号： G02F1/1345

摘要： A liquid crystal display having a plurality of gate lines and a plurality of data lines extending in row and column directions, respectively, are formed on a panel. A switching device connected to the gate line and the data line and a pixel electrode connected thereto are provided in each of pixel areas partitioned by the gate lines and data lines. A data driving circuit and a data driving circuit are also provided on the panel, and apply voltages to the gate lines. A signal wire connected to the data driving circuit and including a plurality of color signal lines is provided on the panel and connects the data driving circuit to a signal controller of a printed circuit board. A pair of the plurality of color signal lines with differential relationship transmit color signals to the data driving circuit. A distance between the pair of the plurality of color signal lines is smaller than a width of each of the pair of the plurality of color signal lines and a distance between a pair of plurality of color signal lines without differential relationship. This relationship of the distances between the signal lines and the width thereof reduces the EMI noise.

摘要翻译： 在面板上形成具有多条栅极线和分别沿列和列方向延伸的多条数据线的液晶显示器。 连接到栅极线和数据线的开关器件和连接到其的像素电极设置在由栅极线和数据线分隔的每个像素区域中。 数据驱动电路和数据驱动电路也设置在面板上，并向栅极线施加电压。 连接到数据驱动电路并且包括多个彩色信号线的信号线被提供在面板上，并将数据驱动电路连接到印刷电路板的信号控制器。 具有差分关系的一对多个彩色信号线将彩色信号传输到数据驱动电路。 所述多个彩色信号线对之间的距离小于所述一对彩色信号线中的每一个的宽度和一对多个彩色信号线之间的距离，而没有差别关系。 信号线之间的距离与其宽度的这种关系降低了EMI噪声。

公开(公告)号：US20080251939A1

公开(公告)日：2008-10-16

申请号：US12100359

申请日：2008-04-09

申请人： Hyun-Soo Chung ,  Dong-Ho Lee ,  Nam-Seog Kim ,  Son-Kwan Hwang

发明人： Hyun-Soo Chung ,  Dong-Ho Lee ,  Nam-Seog Kim ,  Son-Kwan Hwang

IPC分类号： H01L23/498

CPC分类号： H01L23/525 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/01049

摘要： A chip stack package is provided, wherein semiconductor chips having different die sizes are stacked by arranging pads in a scribe region through a redistribution process, so that the thickness of the package can be reduced. A method of fabricating the chip stack package is also provided. In the chip stack package, a plurality of circuit patterns are arranged on one surface of a substrate, and a unit semiconductor chip is mounted thereon. The unit semiconductor chip includes a plurality of semiconductor chips sequentially stacked on the substrate. The semiconductor chips of the unit semiconductor chip have different die sizes. One of the semiconductor chips includes a plurality of first pads arranged in a first chip region, and the other semiconductor chips include second pads arranged in a scribe region at an outside of a second chip region defined by the scribe region.

摘要翻译： 提供了一种芯片堆叠封装，其中具有不同管芯尺寸的半导体芯片通过经由再分配工艺在划线区域中布置衬垫来堆叠，从而可以减小封装的厚度。 还提供了一种制造芯片堆叠封装的方法。 在芯片堆叠封装中，在基板的一个表面上布置多个电路图案，并且在其上安装单元半导体芯片。 单元半导体芯片包括顺序堆叠在基板上的多个半导体芯片。 单元半导体芯片的半导体芯片具有不同的管芯尺寸。 半导体芯片中的一个包括布置在第一芯片区域中的多个第一焊盘，并且其它半导体芯片包括布置在由划线区域限定的第二芯片区域的外侧的划线区域中的第二焊盘。

公开(公告)号：US20080169545A1

公开(公告)日：2008-07-17

申请号：US11790173

申请日：2007-04-24

申请人： Yong-Chai Kwon ,  Dong-Ho Lee ,  Myung-Kee Chung ,  Kang-Wook Lee ,  Sun-Won Kang ,  Keum-Hee Ma

发明人： Yong-Chai Kwon ,  Dong-Ho Lee ,  Myung-Kee Chung ,  Kang-Wook Lee ,  Sun-Won Kang ,  Keum-Hee Ma

IPC分类号： H01L23/02 ,  H01L21/00

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/12 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/90 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/83856 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： A stacked structure of semiconductor devices may include a plurality of stacked semiconductor devices, each having an upper surface and a lower surface and one or more via electrodes protruding from the upper surface to the lower surface. The via-electrodes may have upper parts (heads) protruding from the upper surface and lower parts (ends) protruding from the lower surface. The stacked semiconductor devices may be electrically connected to each other through the via-electrodes. A first adhesive film (e.g., patternable material) and a second adhesive film (e.g. puncturable material) may be formed between the stacked semiconductor devices. The stacked structure of semiconductor devices may be mounted on the upper surface of a printed circuit board (PCB) having a mount-specific adhesive film to form a semiconductor device package. The mounted stacked structure and the upper surface of the PCB may be further covered with a molding material.

摘要翻译： 半导体器件的层叠结构可以包括多个层叠的半导体器件，每个具有上表面和下表面以及从上表面到下表面突出的一个或多个通孔电极。 通孔电极可以具有从上表面突出的上部（头）和从下表面突出的下部（端部）。 层叠的半导体器件可以通过通孔电极彼此电连接。 可以在层叠的半导体器件之间形成第一粘合膜（例如，可图案化材料）和第二粘合膜（例如可刺穿材料）。 半导体器件的堆叠结构可以安装在具有安装专用粘合剂膜的印刷电路板（PCB）的上表面上以形成半导体器件封装。 安装的堆叠结构和PCB的上表面可以进一步被模制材料覆盖。

公开(公告)号：US20070152349A1

公开(公告)日：2007-07-05

申请号：US11355545

申请日：2006-02-15

申请人： Hyun-Soo Chung ,  Ho-Jin Lee ,  Dong-Hyun Jang ,  Dong-Ho Lee

发明人： Hyun-Soo Chung ,  Ho-Jin Lee ,  Dong-Hyun Jang ,  Dong-Ho Lee

IPC分类号： H01L21/00 ,  H01L23/48

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/274 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01079 ,  H01L2924/01087

摘要： In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.

摘要翻译： 在具有应力消除间隔物的半导体器件封装及其制造方法中，从芯片本体延伸的金属互连指状物提供芯片互连。 金属手指通过应力消除间隔物与芯片的主体隔离。 在一个示例中，这种隔离采取气隙的形式。 在另一个实例中，这种隔离采用弹性体材料的形式。 在这两种情况下，都避免了金属互连指和芯体之间的热膨胀系数的不匹配，从而减轻了与开裂和分层相关的问题，从而提高了器件的产量和器件的可靠性。