公开(公告)号：US09716153B2

公开(公告)日：2017-07-25

申请号：US13539459

申请日：2012-07-01

Applicant: Sagy Levy ,  Fredrick Jenne ,  Krishnaswamy Ramkumar

Inventor： Sagy Levy ,  Fredrick Jenne ,  Krishnaswamy Ramkumar

IPC: H01L29/792 ,  H01L29/40 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/408 ,  H01L21/28282 ,  H01L29/04 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/792 ,  H01L29/7926

Abstract: Scaling a charge trap memory device and the article made thereby. In one embodiment, the charge trap memory device includes a substrate having a source region, a drain region, and a channel region electrically connecting the source and drain. A tunnel dielectric layer is disposed above the substrate over the channel region, and a multi-layer charge-trapping region disposed on the tunnel dielectric layer. The multi-layer charge-trapping region includes a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer and a second nitride layer.

公开(公告)号：US09431549B2

公开(公告)日：2016-08-30

申请号：US13436875

申请日：2012-03-31

Applicant: Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

Inventor： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

IPC: H01L29/792 ,  B82Y10/00 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L29/7923 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/11578 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66833 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/792 ,  H01L29/7926

Abstract: An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the split charge-trapping region. The split charge-trapping region includes a first charge-trapping layer comprising a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The multi-layer blocking dielectric comprises at least a high-K dielectric layer.

Abstract translation: 描述了非易失性电荷陷阱存储器件的实施例。 在一个实施例中，该装置包括一个通道，该沟道包括覆盖在电连接存储器件的第一扩散区和第二扩散区的衬底上的表面的硅以及与沟道的至少一部分相交并且覆盖的栅极堆，栅极 包括邻接通道的隧道氧化物的堆叠，邻接隧道氧化物的分裂电荷捕获区域和与分离的电荷捕获区域邻接的多层阻挡电介质。 分离电荷捕获区域包括第一电荷捕获层，其包含更接近隧道氧化物的氮化物，以及包含覆盖在第一电荷俘获层上的氮化物的第二电荷俘获层。 多层阻挡电介质至少包括高K电介质层。

公开(公告)号：US08940645B2

公开(公告)日：2015-01-27

申请号：US13539458

申请日：2012-07-01

Applicant: Krishnaswamy Ramkumar ,  Sagy Levy ,  Jeong Byun

Inventor： Krishnaswamy Ramkumar ,  Sagy Levy ,  Jeong Byun

IPC: H01L21/31

CPC classification number: H01L29/7926 ,  B82Y10/00 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02271 ,  H01L21/02326 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28282 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/775

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a polysilicon channel, and forming over the tunnel oxide layer a multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride, and an oxygen-lean, second layer comprising a nitride on the first layer. The substrate is then subjected to a second oxidation process to consume a portion of the second layer and form a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The stoichiometric composition of the first layer results in it being substantially trap free, and the stoichiometric composition of the second layer results in it being trap dense. The second oxidation process can comprise a plasma oxidation process or a radical oxidation process using In-Situ Steam Generation.

Abstract translation: 描述了制造非易失性电荷陷阱存储器件的方法。 所述方法包括使衬底经受第一氧化工艺以形成覆盖多晶硅沟道的隧道氧化物层，以及在所述隧道氧化物层上形成多层电荷存储层，所述多层电荷存储层包含富氧的第一层，所述第一层包含氮化物，以及 在第一层上包含氮化物的贫氧第二层。 然后对衬底进行第二氧化处理以消耗第二层的一部分并形成覆盖多层电荷存储层的高温氧化物（HTO）层。 第一层的化学计量组成导致其基本上无陷阱，并且第二层的化学计量组成使其陷入致密。 第二氧化过程可以包括使用原位蒸汽发生的等离子体氧化过程或自由基氧化过程。

公开(公告)号：US08859374B1

公开(公告)日：2014-10-14

申请号：US13288919

申请日：2011-11-03

Applicant: Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

Inventor： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

IPC: H01L21/336

CPC classification number: H01L29/513 ,  G11C16/0466 ,  G11C16/349 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/28035 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

Abstract: Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the method comprises: (i) forming an oxide-nitride-oxide (ONO) dielectric stack on a surface of a semiconductor substrate in at least a first region in which a non-volatile memory transistor is to be formed, the ONO dielectric stack including a multi-layer charge storage layer; (ii) forming an oxide layer on the surface of the substrate in a second region in which a metal oxide semiconductor (MOS) logic transistor is to be formed; and (iii) forming a high work function gate electrode on a surface of the ONO dielectric stack. Other embodiments are also disclosed.

Abstract translation: 提供包括非易失性存储晶体管的半导体器件及其制造方法以改善其性能。 在一个实施例中，该方法包括：（i）在其中将形成非易失性存储晶体管的至少第一区域中，在半导体衬底的表面上形成氧化物 - 氧化物 - 氧化物（ONO）电介质叠层， ONO电介质堆叠包括多层电荷存储层; （ii）在要形成金属氧化物半导体（MOS）逻辑晶体管的第二区域中在所述衬底的表面上形成氧化物层; 和（iii）在ONO电介质叠层的表面上形成高功函数栅电极。 还公开了其他实施例。

公开(公告)号：US08710579B1

公开(公告)日：2014-04-29

申请号：US13551237

申请日：2012-07-17

Applicant: Fredrick Jenne ,  Krishnaswamy Ramkumar

Inventor： Fredrick Jenne ,  Krishnaswamy Ramkumar

IPC: H01L29/792

CPC classification number: H01L21/28282 ,  G11C16/04 ,  H01L21/022 ,  H01L21/02323 ,  H01L27/11563 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/792

Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, semiconductor device comprises a split charge-trapping region comprising two nitride layers with charge traps distributed therein, the two nitride layers separated by one or more oxide layers. The two nitride layers include a first nitride layer closer to a substrate over which the split charge-trapping region is formed, and a second nitride layer on the other side of the one or more oxide layers. The second nitride layer comprises a majority of the charge traps. Other embodiments are also described.

Abstract translation: 提供半导体器件及其制造方法。 在一个实施例中，半导体器件包括分离的电荷捕获区域，其包括分布有电荷陷阱的两个氮化物层，两个氮化物层由一个或多个氧化物层分隔开。 两个氮化物层包括更靠近其上形成有分离电荷捕获区的衬底的第一氮化物层和在一个或多个氧化物层的另一侧上的第二氮化物层。 第二氮化物层包括大部分电荷阱。 还描述了其它实施例。

公开(公告)号：US08679927B2

公开(公告)日：2014-03-25

申请号：US12185751

申请日：2008-08-04

Applicant: Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy

Inventor： Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy

IPC: H01L29/792

CPC classification number: H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/7843

Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

Abstract translation: 一种半导体结构及其形成方法。 半导体结构包括具有设置在第一区域上的非易失性电荷陷阱存储器件和设置在第二区域上的逻辑器件的衬底。 可以在形成逻辑器件的阱和通道之后形成电荷陷阱电介质叠层。 可以避免HF预清洗和SC1清洁，以提高非挥发性电荷陷阱存储器件的阻挡层的质量。 在逻辑MOS栅极绝缘体层的热氧化或氮化期间，阻挡层可以被热再氧化或氮化，以致密封阻挡层。 可以使用多层衬垫来首先在高压逻辑器件中偏置源极和漏极注入，并且还阻挡非易失性电荷陷阱存储器件的硅化。

公开(公告)号：US08536640B2

公开(公告)日：2013-09-17

申请号：US11904474

申请日：2007-09-26

Applicant: Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  William W. Koutny

Inventor： Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  William W. Koutny

IPC: H01L29/792

CPC classification number: H01L29/66833 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/511 ,  H01L29/792

Abstract: A nonvolatile charge trap memory device with deuterium passivation of charge traps and method of manufacture. Deuterated gate layer, deuterated gate cap layer and deuterated spacers are employed in various combinations to encapsulate the device with deuterium sources proximate to the interfaces within the gate stack and on the surface of the gate stack where traps may be present.

公开(公告)号：US20130175600A1

公开(公告)日：2013-07-11

申请号：US13431069

申请日：2012-03-27

Applicant: Fredrick Jenne ,  Krishnaswamy Ramkumar

Inventor： Fredrick Jenne ,  Krishnaswamy Ramkumar

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  B82Y10/00 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/785 ,  H01L29/7926

Abstract: Embodiments of a non-planar memory device including a split charge-trapping region and methods of forming the same are described. Generally, the device comprises: a channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide overlying the channel; a split charge-trapping region overlying the tunnel oxide, the split charge-trapping region including a bottom charge-trapping layer comprising a nitride closer to the tunnel oxide, and a top charge-trapping layer, wherein the bottom charge-trapping layer is separated from the top charge-trapping layer by a thin anti-tunneling layer comprising an oxide. Other embodiments are also disclosed.

Abstract translation: 描述了包括分离电荷捕获区域的非平面存储器件及其形成方法的实施例。 通常，该器件包括：由覆盖存储器件的源极和漏极的衬底上的表面的半导体材料薄膜形成的沟道; 覆盖通道的隧道氧化物; 分离电荷捕获区域，覆盖隧道氧化物，分离电荷捕获区域包括底部电荷捕获层，其包含更接近隧道氧化物的氮化物，以及顶部电荷捕获层，其中底部电荷捕获层被分离 从顶部的电荷捕获层通过包含氧化物的薄的抗隧道层。 还公开了其他实施例。

公开(公告)号：US08093128B2

公开(公告)日：2012-01-10

申请号：US12125864

申请日：2008-05-22

Applicant: William W. C. Koutny, Jr. ,  Sam Geha ,  Igor Kouznetsov ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy ,  Ravindra Kapre ,  Jeremy Warren

Inventor： William W. C. Koutny, Jr. ,  Sam Geha ,  Igor Kouznetsov ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy ,  Ravindra Kapre ,  Jeremy Warren

IPC: H01L29/792

CPC classification number: H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/7843

Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

公开(公告)号：US08088683B2

公开(公告)日：2012-01-03

申请号：US12080166

申请日：2008-03-31

Applicant: Krishnaswamy Ramkumar ,  Sagy Levy

Inventor： Krishnaswamy Ramkumar ,  Sagy Levy

IPC: H01L21/4763

CPC classification number: H01L21/28282 ,  H01L21/3145

Abstract: Deposition and anneal operations are iterated to break a deposition into a number of sequential deposition-anneal operations to reach a desired annealed dielectric layer thickness. In one particular embodiment, a two step anneal is performed including an NH3 or ND3 ambient followed by an N2O or NO ambient. In one embodiment, such a method is employed to form a dielectric layer having a stoichiometry attainable with only a deposition process but with a uniform material quality uncharacteristically high of a deposition process. In particular embodiments, sequential deposition-anneal operations provide an annealed first dielectric layer upon which a second dielectric layer may be left substantially non-annealed.

Abstract translation: 重复沉积和退火操作以将沉积破坏成多个顺序的沉积退火操作以达到期望的退火介电层厚度。 在一个具体实施方案中，进行包括NH 3或ND 3环境，随后是N 2 O或NO环境的两步退火。 在一个实施例中，采用这种方法形成具有仅通过沉积工艺可获得的化学计量但具有均匀材料质量的电介质层，这在沉积过程中具有非常高的特性。 在特定实施例中，顺序沉积 - 退火操作提供退火的第一介电层，第二介电层可以在其上基本上保持不退火。