公开(公告)号：US20130250685A1

公开(公告)日：2013-09-26

申请号：US13903923

申请日：2013-05-28

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C16/04

CPC分类号： G11C14/0018 ,  G11C11/404 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/225 ,  G11C2211/4016 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7885 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

公开(公告)号：US08531881B2

公开(公告)日：2013-09-10

申请号：US13462702

申请日：2012-05-02

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C14/00

CPC分类号： G11C11/4026 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0097 ,  G11C14/0018 ,  G11C14/0045 ,  G11C16/0416 ,  G11C2211/4016 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/1023 ,  H01L27/1052 ,  H01L27/10802 ,  H01L27/24 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/7881 ,  H01L45/06 ,  H01L45/144 ,  H01L45/145

摘要： In at least one embodiment, a memory cell includes a substrate having a top surface and a first conductivity type; a first region having a second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

摘要翻译： 在至少一个实施例中，存储单元包括具有顶表面和第一导电类型的衬底; 具有与第一导电类型不同的第二导电类型的第一区域，第一区域形成在基板中并在顶表面露出; 具有第二导电类型的第二区域形成在基板中，与第一区域间隔开并暴露在顶表面处; 位于第一和第二区域下方的衬底中的与第一和第二区域间隔开并且具有第二导电类型的掩埋层; 形成在所述第一和第二区域与所述掩埋层之间的体区; 位于第一和第二区域之间并位于顶部表面之上的门; 以及非易失性存储器，被配置为在从身体区域传送时存储数据。

公开(公告)号：US08514623B2

公开(公告)日：2013-08-20

申请号：US13478014

申请日：2012-05-22

申请人： Yuniarto Widjaja ,  Zvi Or-Bach

发明人： Yuniarto Widjaja ,  Zvi Or-Bach

IPC分类号： G11C14/00

CPC分类号： H01L27/10802 ,  G11C7/00 ,  G11C11/404 ,  G11C11/4067 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4099 ,  G11C11/565 ,  G11C14/0018 ,  G11C16/0416 ,  G11C2211/4016 ,  H01L27/1023 ,  H01L27/108 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7395 ,  H01L29/7455 ,  H01L29/7841 ,  H01L29/7881

摘要： Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

公开(公告)号：US08391066B2

公开(公告)日：2013-03-05

申请号：US13231188

申请日：2011-09-13

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C14/00

CPC分类号： H01L27/10802 ,  G11C11/40 ,  G11C11/404 ,  G11C14/0018 ,  G11C16/0416 ,  G11C2211/4016 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7881

摘要： Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a substrate, a floating body to store data in volatile memory and a floating gate or trapping layer configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell.

摘要翻译： 具有易失性和非易失性模式和操作方法的半导体存储器。 半导体存储单元包括基板，用于将数据存储在易失性存储器中的浮动体和浮置栅极或俘获层，其被配置为接收由易失性存储器存储的数据的传送，并将数据作为非易失性存储器存储在浮动栅极或俘获层中 中断存储单元的电源。

公开(公告)号：US20130015517A1

公开(公告)日：2013-01-17

申请号：US13577282

申请日：2011-02-07

申请人： Yuniarto Widjaja ,  Zvi Or-Bach

发明人： Yuniarto Widjaja ,  Zvi Or-Bach

IPC分类号： H01L29/788

CPC分类号： G11C14/0018 ,  G11C11/404 ,  G11C11/565 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/06 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/788 ,  H01L29/7881

摘要： A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.

摘要翻译： 半导体存储单元包括被配置为被充电到指示存储单元的状态的电平的浮动体区域; 与所述浮体区域电接触的第一区域; 与所述浮体区域电接触并与所述第一区域间隔开的第二区域; 以及位于所述第一和第二区域之间的门。 单元可以是多级单元。 公开了用于制造存储器件的存储器单元阵列。 还提供了操作存储单元的方法。

公开(公告)号：US20120241708A1

公开(公告)日：2012-09-27

申请号：US13462702

申请日：2012-05-02

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： H01L47/00

CPC分类号： G11C11/4026 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0097 ,  G11C14/0018 ,  G11C14/0045 ,  G11C16/0416 ,  G11C2211/4016 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/1023 ,  H01L27/1052 ,  H01L27/10802 ,  H01L27/24 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/7881 ,  H01L45/06 ,  H01L45/144 ,  H01L45/145

摘要： In at least one embodiment, a memory cell includes a substrate having a top surface and a first conductivity type; a first region having a second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

摘要翻译： 在至少一个实施例中，存储单元包括具有顶表面和第一导电类型的衬底; 具有与第一导电类型不同的第二导电类型的第一区域，第一区域形成在基板中并在顶表面露出; 具有第二导电类型的第二区域形成在基板中，与第一区域间隔开并暴露在顶表面处; 位于第一和第二区域下方的衬底中的与第一和第二区域间隔开并且具有第二导电类型的掩埋层; 形成在所述第一和第二区域与所述掩埋层之间的体区; 位于第一和第二区域之间并位于顶部表面之上的门; 以及非易失性存储器，被配置为在从身体区域传送时存储数据。

公开(公告)号：US20120217549A1

公开(公告)日：2012-08-30

申请号：US13244899

申请日：2011-09-26

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： H01L27/10

CPC分类号： H01L27/10802 ,  G11C11/404 ,  G11C2211/4016 ,  H01L29/7308 ,  H01L29/7841

摘要： Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side.

摘要翻译： 描述了非对称的，半导体存储器单元，阵列，器件和方法。 其中，描述了一种不对称的双稳态半导体存储单元，其包括：被配置为被充电到指示存储单元的状态的电平的浮动体区域; 与所述浮体区域电接触的第一区域; 与所述浮体区域电接触并与所述第一区域间隔开的第二区域; 以及位于所述第一和第二区域之间的门，使得所述第一区域相对于所述栅极位于所述存储器单元的第一侧上，并且所述第二区域相对于所述栅极位于所述存储器单元的第二侧上; 其中第一侧的性能特性不同于第二侧的性能特性。

公开(公告)号：US08194471B2

公开(公告)日：2012-06-05

申请号：US13245220

申请日：2011-09-26

申请人： Yuniarto Widjaja ,  Zvi Or-Bach

发明人： Yuniarto Widjaja ,  Zvi Or-Bach

IPC分类号： G11C7/00

CPC分类号： H01L27/10802 ,  G11C7/22 ,  G11C11/04 ,  G11C11/39 ,  G11C11/4026 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096 ,  G11C14/0018 ,  G11C2211/4016 ,  H01L23/528 ,  H01L29/1095 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/772 ,  H01L29/7841 ,  H01L29/7881

摘要： A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type.

摘要翻译： 一种用于对具有行和列的存储器单元的半导体存储器阵列进行保持操作的方法，包括：将电信号施加到存储器单元的掩埋区域，其中每个存储器单元包括限定至少一部分的浮体区域 所述浮体区域具有第一导电类型; 并且其中每个存储单元的所述埋入区位于所述存储单元内并且位于所述浮体区附近，所述掩埋区具有第二导电类型。

公开(公告)号：US20110305085A1

公开(公告)日：2011-12-15

申请号：US13196471

申请日：2011-08-02

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C14/00

CPC分类号： G11C14/0018 ,  G11C11/5671 ,  G11C14/00 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/0475 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/115 ,  H01L29/7841 ,  H01L29/792

摘要： A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another, and a control gate positioned above the trapping layer.

摘要翻译： 描述了半导体存储单元，包括多个半导体存储单元的半导体存储器件以及使用该半导体存储单元和器件的方法。 半导体存储单元包括具有第一导电类型的衬底; 第一区域，其在衬底的第一位置处嵌入衬底并具有第二导电类型; 第二区域，其在衬底的第二位置处嵌入在衬底中并具有第二导电类型，使得具有第一导电类型的衬底的至少一部分位于第一和第二位置之间，并且用作浮体 将数据存储在易失性存储器中; 位于所述第一位置和所述第二位置之间并位于所述衬底的表面之上的捕获层; 包括第一和第二存储位置的捕获层被配置为将数据彼此独立地存储为非易失性存储器，以及位于捕获层上方的控制栅极。

公开(公告)号：US20110228591A1

公开(公告)日：2011-09-22

申请号：US13116924

申请日：2011-05-26

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C11/40

CPC分类号： G11C14/0045 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0685 ,  G11C11/14 ,  G11C11/404 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0033 ,  G11C2013/0045 ,  G11C2013/0078 ,  G11C2211/4016 ,  G11C2211/5643 ,  G11C2213/31 ,  G11C2213/32 ,  H01L27/1023 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10897 ,  H01L27/24 ,  H01L27/2445 ,  H01L27/2463 ,  H01L29/7841 ,  H01L45/06 ,  H01L45/065 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147

摘要： Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

摘要翻译： 提供半导体存储器，其中存储单元包括具有浮动体的无电容器晶体管，其被配置为当向单元施加电力时将数据作为电荷存储在其中。 电池还包括非易失性存储器，其包括电阻变化元件，电阻变化元件被配置为在多个预定条件中的任何一个下存储存储在浮动体中的数据。 描述了一种操作半导体存储器以用作易失性存储器的方法，同时当功率停止到半导体存储器时具有保留存储数据的能力。