Semiconductor device
    61.
    发明授权

    公开(公告)号:US12051743B2

    公开(公告)日:2024-07-30

    申请号:US17163982

    申请日:2021-02-01

    申请人: ROHM CO., LTD.

    发明人: Masaki Nagata

    摘要: There is provided a semiconductor device, including: a semiconductor chip including a main surface; a gate trench formed on the main surface; a first insulating film configured to cover an upper wall surface of the gate trench; a second insulating film configured to cover a lower wall surface of the gate trench; a field trench formed on the main surface so as to be spaced apart from the gate trench, and including a facing wall at a side of the gate trench and a non-facing wall at an opposite side of the facing wall; a third insulating film configured to cover an upper wall surface of the field trench at a side of the facing wall; and a fourth insulating film configured to cover a lower wall surface of the field trench at the side of the facing wall and the non-facing wall.

    Semiconductor device, OTP readout circuit, and OTP circuit

    公开(公告)号:US12046311B2

    公开(公告)日:2024-07-23

    申请号:US17568472

    申请日:2022-01-04

    申请人: ROHM CO., LTD.

    发明人: Seiji Takenaka

    IPC分类号: G11C17/18 G11C17/16

    CPC分类号: G11C17/18 G11C17/16

    摘要: An OTP readout circuit includes an OTP circuit having a first OTP cell in which data is programmable only once, and a readout-possible signal output unit configured to generate a readout-possible voltage for reading out the data and output the generated readout-possible voltage to the OTP circuit. The readout-possible voltage from the readout-possible signal output unit causes the OTP circuit to read out the data programmed into the first OTP cell.

    SSH CIRCUIT AND ELECTRONIC DEVICE
    67.
    发明公开

    公开(公告)号:US20240243717A1

    公开(公告)日:2024-07-18

    申请号:US18413268

    申请日:2024-01-16

    申请人: ROHM Co., LTD.

    IPC分类号: H03H7/01

    CPC分类号: H03H7/0115

    摘要: An SSH circuit includes a plurality of unit lattices, each unit lattice including unit circuits. Each unit circuit includes two first inductors, a second inductor connected in series between the two first inductors, and two capacitors connected between a ground potential and two respective connection nodes at which the first and second inductors are connected to each other, an inductance of the second inductor being larger than that of the first inductors. In each unit lattice, the two connection nodes of each unit circuit are arranged at respective vertexes of both ends of each side forming a hyperrectangle, and the connection nodes arranged at each vertex being connected to each other and sharing the corresponding capacitor. The unit lattices are connected to each other by a mutual sharing of the first inductors by two unit lattices adjacent to each other. A peripheral edge has an uneven shape of unit lattices.

    Semiconductor laser device
    68.
    发明授权

    公开(公告)号:US12040590B2

    公开(公告)日:2024-07-16

    申请号:US17273962

    申请日:2019-09-24

    申请人: ROHM CO., LTD.

    摘要: A semiconductor laser device A1 comprises a semiconductor laser chip 2 and a stem 1. The stem 1 includes a base 11 and leads 3A, 3B, and 3C fixed to the base, and supports the semiconductor laser chip 2. The semiconductor laser device A1 further comprises a first metal layer 15 including a first layer 151 covering the base 11 and the leads 3A, 3B, and 3C, a second layer 152 interposed between the first layer 151 and each of the base 11 and the leads 3A, 3B, and 3C, and a third layer 153 interposed between the second layer 152 and each of the base 11 and the leads 3A, 3B, and 3C. Crystal grains in the second layer 152 are smaller than crystal grains in the third layer 153. Such a configuration can suppress corrosion.

    SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND VEHICLE

    公开(公告)号:US20240235190A1

    公开(公告)日:2024-07-11

    申请号:US18614483

    申请日:2024-03-22

    申请人: Rohm Co., Ltd.

    发明人: Naoki Takahashi

    摘要: A semiconductor device includes: an output transistor of a split-gate type configured to have a plurality of channel regions controlled individually according to a plurality of gate control signals; an active clamp circuit configured to limit the terminal-to-terminal voltage across the output transistor to or below a predetermined clamp voltage after a control signal turns to a logic level requesting the output transistor to be off; a delay circuit configured to generate a delayed internal signal by giving a predetermined delay to an internal signal indicating whether the terminal-to-terminal voltage across the output transistor is higher than a predetermined threshold voltage lower than the clamp voltage; and a gate control circuit configured to control the plurality of gate control signals individually so as to raise the on resistance of the output transistor according to the delayed internal signal.