公开(公告)号：US20110254060A1

公开(公告)日：2011-10-20

申请号：US12760782

申请日：2010-04-15

申请人： Yu-Ru YANG ,  Tzung-Ying Lee ,  Chin-Fu Lin ,  Chi-Mao Hsu

发明人： Yu-Ru YANG ,  Tzung-Ying Lee ,  Chin-Fu Lin ,  Chi-Mao Hsu

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L29/518 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78

摘要： A method of fabricating a metal gate structure is provided. Firstly, a high-K gate dielectric layer is formed on a semiconductor substrate. Then, a first metal-containing layer having a surface away from the gate dielectric layer is formed on the gate dielectric layer. After that, the surface of the first metal-containing layer is treated to improve the nitrogen content thereof of the surface. Subsequently, a silicon layer is formed on the first metal-containing layer. Because the silicon layer is formed on the surface having high nitrogen content, the catalyzing effect to the silicon layer resulted from the metal material in the first metal-containing layer can be prevented. As a result, the process yield is improved.

摘要翻译： 提供一种制造金属栅极结构的方法。 首先，在半导体衬底上形成高K栅介质层。 然后，在栅极电介质层上形成具有离开栅极电介质层的表面的第一含金属层。 之后，处理第一含金属层的表面以改善其表面的氮含量。 随后，在第一含金属层上形成硅层。 由于在具有高氮含量的表面上形成硅层，所以可以防止由第一含金属层中的金属材料产生的对硅层的催化作用。 结果，工艺产量提高。

公开(公告)号：US20110195636A1

公开(公告)日：2011-08-11

申请号：US12703998

申请日：2010-02-11

申请人： Ji-Gang PAN

发明人： Ji-Gang PAN

IPC分类号： B24B51/00 ,  B24B49/00 ,  B24B49/06

CPC分类号： B24B37/005 ,  B24B37/042 ,  G05B2219/45232 ,  H01L22/26

摘要： A method for controlling polishing a wafer includes the following step. Firstly, a database storing a number of status data of a polished film of a wafer and a number of polishing parameters corresponding to the status data is established. Each of the polishing parameters includes a head sweep of a polishing head along a redial direction of a polishing platen. The head sweep refers to a movement distance range from a center of the polishing head to a center of the polishing platen during a polishing process. Subsequently, a first wafer having a predetermined status data is provided. Thereafter, the predetermined status data is compared with the status data in the database so as to find out the polishing parameter corresponding to the predetermined status data, thereby determining a first polishing parameter of the first wafer. Afterward, a first polishing process using the first polishing parameter is applied to the first wafer. The method can control the status of a polished film and optimize the polishing parameter.

摘要翻译： 控制抛光晶片的方法包括以下步骤。 首先，建立存储晶片的抛光膜的状态数据的数据和与状态数据对应的多个研磨参数的数据库。 每个抛光参数包括抛光头沿着抛光台板的重拨方向的头扫。 头部扫掠是指在抛光处理期间从抛光头的中心到研磨台板的中心的移动距离范围。 随后，提供具有预定状态数据的第一晶片。 此后，将预定状态数据与数据库中的状态数据进行比较，以找出与预定状态数据对应的抛光参数，由此确定第一晶片的第一抛光参数。 之后，使用第一抛光参数的第一抛光工艺被施加到第一晶片。 该方法可以控制抛光膜的状态并优化抛光参数。

公开(公告)号：US20110193586A1

公开(公告)日：2011-08-11

申请号：US12703949

申请日：2010-02-11

申请人： Sung-Nien Kuo ,  Yuan-Yu Hsieh ,  Wen-Hsiung Ko ,  Jih-San Lee ,  Kuei-Chi Juan ,  Kuan-Cheng Su

发明人： Sung-Nien Kuo ,  Yuan-Yu Hsieh ,  Wen-Hsiung Ko ,  Jih-San Lee ,  Kuei-Chi Juan ,  Kuan-Cheng Su

IPC分类号： G01R31/26 ,  G01R31/02

CPC分类号： G01R31/2621 ,  G01R31/2642 ,  G01R31/2849 ,  H01L22/34

摘要： An AC stress test circuit for HCI degradation evaluation in semiconductor devices includes a ring oscillator circuit, first and second pads, and first and second isolating switches. The ring oscillator circuit has a plurality of stages connected in series to form a loop. Each of the stages comprises a first node and a second node. The first and second isolating switches respectively connect the first and second pads to the first and second nodes of a designated stage and both are switched-off during ring oscillator stressing of the designated stage. The present invention also provides a method of evaluating AC stress induced HCI degradation, and a test structure.

摘要翻译： 用于半导体器件中的HCI劣化评估的AC应力测试电路包括环形振荡器电路，第一和第二焊盘以及第一和第二隔离开关。 环形振荡器电路具有多个串联连接以形成环路。 每个级包括第一节点和第二节点。 第一和第二隔离开关分别将第一和第二焊盘连接到指定级的第一和第二节点，并且在指定阶段的环形振荡器应力期间两者都被切断。 本发明还提供了一种评估AC应力诱导的HCI降解的方法和测试结构。

公开(公告)号：US20110189859A1

公开(公告)日：2011-08-04

申请号：US12696055

申请日：2010-01-29

申请人： Ping-Chia Shih ,  Yu-Cheng Wang ,  Chun-Sung Huang ,  Yuan-Cheng Yang ,  Chung-Che Huang ,  Chin-Fu Lin

发明人： Ping-Chia Shih ,  Yu-Cheng Wang ,  Chun-Sung Huang ,  Yuan-Cheng Yang ,  Chung-Che Huang ,  Chin-Fu Lin

IPC分类号： H01L21/311

CPC分类号： H01L21/311

摘要： An exemplary method of etching an oxide layer and a nitride layer is provided. In particular, a substrate is provided. A surface of the substrate has an isolating structure projecting therefrom. A first oxide layer, a nitride layer and a second oxide layer are sequentially provided on the surface of the substrate, wherein the first oxide layer is uncovered on the isolating structure, the nitride layer is formed overlying the first oxide layer, and the second oxide layer is formed overlying the nitride layer. An isotropic etching process is performed by using an etching mask unmasking the isolating structure, and thereby removing the unmasked portion of the second oxide layer and the unmasked portion of the nitride layer and further exposing sidewalls of the isolating structure. The unmasked portion of the first oxide layer generally is partially removed due to over-etching.

摘要翻译： 提供蚀刻氧化物层和氮化物层的示例性方法。 特别地，提供了基板。 基板的表面具有从其突出的隔离结构。 第一氧化物层，氮化物层和第二氧化物层依次设置在衬底的表面上，其中第一氧化物层未被覆盖在隔离结构上，氮化物层形成在第一氧化物层上，第二氧化物 层叠在氮化物层上。 通过使用非掩蔽隔离结构的蚀刻掩模进行各向同性蚀刻处理，从而去除第二氧化物层的未掩模部分和氮化物层的未掩模部分，并进一步暴露隔离结构的侧壁。 由于过蚀刻，第一氧化物层的未掩模部分通常被部分去除。

公开(公告)号：US07244653B2

公开(公告)日：2007-07-17

申请号：US10807795

申请日：2004-03-23

申请人： Lawrence Liu ,  Yuan Kao

发明人： Lawrence Liu ,  Yuan Kao

IPC分类号： H01L27/76

CPC分类号： H01L27/112 ,  H01L27/1126

摘要： A method and structure of manufacture of mask ROM device is provided. Firstly, a semiconductor structure is provided that comprises a first dielectric layer, a plurality of buried bit lines and a plurality of code areas, wherein each of the code areas is placed between two buried bit lines. Next, a second dielectric layer having a plurality of contact plugs is formed on the semiconductor structure, wherein the contact plug comprises a second dielectric layer and a first glue layer, furthermore; the first glue layer is placed on the side-wall and bottom of the contact plugs. In addition, the contact plugs filled with the first metal layer. Then, a second glue layer, a second metal layer and a pad layer having an opening pattern are respectively formed on the second dielectric layer and contact plug. Thus, the processes of the present invention can improve the stability and accuracy in the electricity of the mask ROM device.

摘要翻译： 提供了掩模ROM器件的制造方法和结构。 首先，提供半导体结构，其包括第一介电层，多个掩埋位线和多个代码区域，其中每个代码区域被放置在两个掩埋位线之间。 接下来，在半导体结构上形成具有多个接触插塞的第二电介质层，其中，所述接触插塞还包括第二电介质层和第一胶合层; 第一胶层位于接触塞的侧壁和底部。 另外，填充有第一金属层的接触塞子。 然后，在第二电介质层和接触插塞上分别形成具有开口图案的第二胶合层，第二金属层和垫层。 因此，本发明的方法可以提高掩模ROM装置的电力的稳定性和精度。

公开(公告)号：US07087464B2

公开(公告)日：2006-08-08

申请号：US10986104

申请日：2004-11-12

申请人： Dylan Yu ,  Gary Guan ,  Jolas Chen ,  Yi-Ming Chang

发明人： Dylan Yu ,  Gary Guan ,  Jolas Chen ,  Yi-Ming Chang

IPC分类号： H01L21/44

CPC分类号： H01L27/14618 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/16195 ,  H01L2924/00014

摘要： A method and structure for a wafer level package is provided, which utilizes a plurality of spacer walls on a semiconductor wafer or a transparent substrate, which has the ability to decide the position of the sealant. As a result, the dimension of a device is decided by the position of the sealant and the spacer walls, therefore, shrinking the distance between the photosensitive zone and the sealant will enhance the gross dies after performing a die sawing process to the whole semiconductor wafer. In addition, the semiconductor process decides the height of the spacer walls so that the yield will be improved due to the fact that a uniformity of the gap, which is between the semiconductor wafer and the transparent substrate, and the width of sealant, will be controlled.

摘要翻译： 提供了一种用于晶片级封装的方法和结构，其利用半导体晶片或透明基板上的多个间隔壁，其具有决定密封剂位置的能力。 结果，装置的尺寸由密封剂和间隔壁的位置决定，因此，在对整个半导体晶片进行模切工艺之后，缩小感光区和密封剂之间的距离将增加总模量 。 此外，半导体工艺决定间隔壁的高度，从而由于半导体晶片和透明基板之间的间隙的均匀性和密封剂的宽度将是 受控。

公开(公告)号：US07064029B2

公开(公告)日：2006-06-20

申请号：US11025903

申请日：2005-01-03

申请人： Hideki Takeuchi ,  Hirohiko Izumi

发明人： Hideki Takeuchi ,  Hirohiko Izumi

IPC分类号： H01L21/8238

CPC分类号： H01L28/91 ,  H01L21/76895

摘要： A semiconductor memory device has access transistors with a gate and a pair of impurity diffusion layers formed on a semiconductor substrate and memory capacitors with a storage node electrode and a cell plate electrode. The electrodes are connected to each other via a capacitive insulating layer made of a ferroelectric material. The storage node electrode has a surface covered with the capacitive insulating layer and is formed in a shape of column on one of the pair of impurity diffusion layers in a hole formed from an inter-layer insulating film covering the access transistor to the one of the pair of impurity diffusion layers. A upper surface of the column does not exceed the inter-layer insulating film. The storage node electrode formed in the hole face the cell plate electrode via the inter-layer insulating film.

公开(公告)号：US20050242377A1

公开(公告)日：2005-11-03

申请号：US11160605

申请日：2005-06-30

申请人： Kohei Eguchi ,  Yuichi Egawa ,  Shoichi Iwasa ,  Hideki Fujikake ,  Wataru Yokozeki ,  Tatsuya Kawamata

发明人： Kohei Eguchi ,  Yuichi Egawa ,  Shoichi Iwasa ,  Hideki Fujikake ,  Wataru Yokozeki ,  Tatsuya Kawamata

IPC分类号： H01L21/761 ,  H01L21/765 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/06 ,  H01L27/115 ,  H01L27/148

CPC分类号： H01L27/11521 ,  H01L21/761 ,  H01L21/765 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1463

摘要： A semiconductor device and a method for manufacturing the same and method for deleting information in use of the semiconductor device, in which field shield isolation or a trench type isolation between elements is used with suppression of penetration of field oxide into element active region of the device, that is, a defect involved in conventional LOGOS type process, are disclosed. A non-LOCOS insulating device isolation block is formed in a semiconductor substrate. The non-LOCOS insulating device isolation block uses a field shield element isolation structure or trench type element isolation structure. After gate electrode wiring layers are formed in a field region and an active region to the same level, a pad polysilicon film formed on the entire surface to cover the patterns of these gate electrode wiring layers is polished by chemical mechanical polishing (CMP) using the cap insulating films of the gate electrode wiring layers as stoppers, thereby forming the gate electrode wiring layers into separated patterns. With this arrangement, even when the width of the gate electrode wiring layer is reduced to the exposure limit in photolithography, the pad polysilicon film can be separated and patterned.

摘要翻译： 半导体器件及其制造方法以及使用半导体器件的信息的删除方法，其中使用场屏蔽隔离或元件之间的沟槽型隔离，同时抑制场氧化物穿透到器件的有源区域 ，也就是说，涉及常规LOGOS型工艺的缺陷。 在半导体衬底中形成非LOCOS绝缘器件隔离块。 非LOCOS绝缘器件隔离块使用场屏蔽元件隔离结构或沟槽型元件隔离结构。 在场区域和有源区域中形成相同电平的栅极电极布线层之后，通过化学机械抛光（CMP）对形成在覆盖这些栅极布线层的图案的整个表面上的焊盘多晶硅膜进行抛光 将栅电极配线层的绝缘膜作为止动器，由此将栅电极配线层形成分离图案。 利用这种布置，即使在光刻中将栅极布线层的宽度减小到曝光极限时，也可以分离和图案化衬垫多晶硅膜。

公开(公告)号：US20050145917A1

公开(公告)日：2005-07-07

申请号：US11025903

申请日：2005-01-03

申请人： Hideki Takeuchi ,  Hirohiko Izumi

发明人： Hideki Takeuchi ,  Hirohiko Izumi

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L29/76

CPC分类号： H01L28/91 ,  H01L21/76895

摘要： A semiconductor memory device has access transistors with a gate and a pair of impurity diffusion layers formed on a semiconductor substrate and memory capacitors with a storage node electrode and a cell plate electrode. The electrodes are connected to each other via a capacitive insulating layer made of a ferroelectric material. The storage node electrode has a surface covered with the capacitive insulating layer and is formed in a shape of column on one of the pair of impurity diffusion layers in a hole formed from an inter-layer insulating film covering the access transistor to the one of the pair of impurity diffusion layers. A upper surface of the column does not exceed the inter-layer insulating film. The storage node electrode formed in the hole face the cell plate electrode via the inter-layer insulating film.

摘要翻译： 半导体存储器件具有存取晶体管，其具有形成在半导体衬底上的栅极和一对杂质扩散层，以及具有存储节点电极和单元板电极的存储电容器。 电极通过由铁电体材料制成的电容绝缘层彼此连接。 存储节点电极具有被电容绝缘层覆盖的表面，并且在由覆盖存取晶体管的层间绝缘膜形成的孔中的一对杂质扩散层中的一个上形成为列的形状 一对杂质扩散层。 柱的上表面不超过层间绝缘膜。 形成在孔中的存储节点电极经由层间绝缘膜与电池板电极相对。

公开(公告)号：US20050072993A1

公开(公告)日：2005-04-07

申请号：US10904496

申请日：2004-11-12

申请人： Hiroyuki Inoue

发明人： Hiroyuki Inoue

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/763 ,  H01L21/00 ,  H01L21/8234 ,  H01L23/52 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/6659 ,  H01L21/763 ,  H01L2924/0002 ,  Y10S257/90 ,  H01L2924/00

摘要： In a semiconductor device in which a source/drain and a wiring layer are connected to each other through an associated buried conductive layer, a separation width of the buried conductive layer on a upper portion of a gate electrode is made small to manufacture a highly reliable and fine MOS transistor. After a silicon oxide film has been formed on a first polycrystalline silicon film to be aligned with a width of a gate electrode, a second polycrystalline silicon film formed on the whole surface of a substrate is selectively etched away so as to be left only on both side faces of a pattern of the silicon oxide film. Thereafter, the first polycrystalline silicon film is selectively etched away with both the silicon oxide film and the second polycrystalline silicon film as an etching mask so that the first polycrystalline film is separated with a width which is smaller than that of the gate electrode by a width of a pattern of the second polycrystalline silicon film. As a result, the buried conductive layer including the first and second polycrystalline silicon films is formed.

摘要翻译： 在通过相关的掩埋导电层将源极/漏极和布线层彼此连接的半导体器件中，使栅极电极上部的掩埋导电层的分离宽度小，制造高可靠性 和精细的MOS晶体管。 在第一多晶硅膜上形成氧化硅膜以与栅电极的宽度对准之后，形成在基板的整个表面上的第二多晶硅膜被选择性地蚀刻掉，以便仅留在两者上 氧化硅膜的图案的侧面。 此后，利用氧化硅膜和第二多晶硅膜作为蚀刻掩模，选择性地蚀刻掉第一多晶硅膜，使得第一多晶硅膜的宽度小于栅极电极的宽度宽度 的第二多晶硅膜的图案。 结果，形成包括第一和第二多晶硅膜的掩埋导电层。