利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

1516 条记录 (耗时 0.031 秒)

    DYNAMIC POWER ROUTING TO HARDWARE ACCELERATORS
    63.
    发明申请
    DYNAMIC POWER ROUTING TO HARDWARE ACCELERATORS 有权
    动力线路到硬件加速器

    公开(公告)号：US20160299553A1

    公开(公告)日：2016-10-13

    申请号：US14682088

    申请日：2015-04-08

    申请人： Microsoft Technology Licensing, LLC

    发明人： Andrew R. Putnam ,  Douglas Christopher Burger ,  Stephen F. Heil ,  Eric S. Chung ,  Adrian M. Caulfield

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3287 ,  G06F1/3293 ,  G06F9/5044 ,  G06F9/5094 ,  G06F2209/509 ,  Y02D10/122 ,  Y02D10/171

    摘要： Dynamic power routing is utilized to route power from other components, which are transitioned to lower power consuming states, in order to accommodate more efficient processing of computational tasks by hardware accelerators, thereby staying within electrical power thresholds that would otherwise not have accommodated simultaneous full-power operation of the other components and such hardware accelerators. Once a portion of a workflow is being processed by hardware accelerators, the workflow, or the hardware accelerators, can be self-throttling to stay within power thresholds, or they can be throttled by independent coordinators, including device-centric and system-wide coordinators. Additionally, predictive mechanisms can be utilized to obtain available power in advance, by proactively transitioning other components to reduced power consuming states, or reactive mechanisms can be utilized to only transition components to reduced power consuming states when a specific need for increased hardware accelerator power is identified.

    摘要翻译： 动态功率路由用于将功率从其他组件转移到低功耗状态，以便通过硬件加速器来适应计算任务的更有效的处理，从而保持在电源阈值内，否则， 其他组件和这种硬件加速器的电源操作。 一旦工作流的一部分正在由硬件加速器处理，工作流程或硬件加速器可以自我调节以保持在电源阈值内，或者可以由独立协调器（包括以设备为中心的和全系统的协调器）进行限制 。 另外，可以利用预测机制来预先获得可用功率，主动地将其它组件转换到降低的功耗状态，或者当特定需要增加的硬件加速器功率时，反应机制可以仅用于将组件转换到降低的功耗状态 确定。

    Wakeup detector
    64.
    发明授权
    Wakeup detector 有权
    唤醒检测器

    公开(公告)号：US09454212B1

    公开(公告)日：2016-09-27

    申请号：US14563633

    申请日：2014-12-08

    申请人： Western Digital Technologies, Inc.

    发明人： Martin E. Schulze

    IPC分类号： G06F1/26 ,  G06F1/32 ,  G06F1/12

    CPC分类号： G06F1/324 ,  G06F1/12 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/126

    摘要： Systems and methods related to wakeup circuits for electronic devices are disclosed. More particularly, an electronic device includes a component operable in at least a lower power state and a higher power state and a wakeup circuit configured to signal the component to transition from the lower power state to the higher power state upon declaration of a wakeup event. The wakeup circuit is configured to process a received input signal to synchronize with a clock; generate an activity signal that includes an activity pulse for each time the processed input signal changes state in different cycles of the clock; open a qualification window upon detection of a first activity pulse in the activity signal; and in the event more than a threshold number of activity pulses in the activity signal are detected prior to closing the qualification window, declare a wakeup event.

    摘要翻译： 公开了与电子设备的唤醒电路相关的系统和方法。 更具体地，电子设备包括可操作在至少较低功率状态和较高功率状态的组件以及被配置为在声明唤醒事件时将组件从较低功率状态转换到较高功率状态的唤醒电路。 唤醒电路被配置为处理接收的输入信号以与时钟同步; 产生活动信号，其中每当处理的输入信号在时钟的不同周期中改变状态时，其包括活动脉冲; 在检测到活动信号中的第一活动脉冲时，打开限定窗口; 并且在关闭限定窗口之前检测到活动信号中的多于一个阈值数量的活动脉冲的情况下，声明一个唤醒事件。

    Systems and methods for messaging-based fine granularity system-on-a-chip power gating
    65.
    发明授权
    Systems and methods for messaging-based fine granularity system-on-a-chip power gating 有权
    基于消息传递的精细粒度系统片上电源门控的系统和方法

    公开(公告)号：US09448617B2

    公开(公告)日：2016-09-20

    申请号：US14204555

    申请日：2014-03-11

    申请人： FutureWei Technologies, Inc.

    发明人： Mark Brown ,  Mehran Bagheri ,  Peter Yan ,  Alan Gatherer

    IPC分类号： G06F1/32 ,  G06F13/40 ,  G06F9/44

    CPC分类号： G06F1/3293 ,  G06F1/3243 ,  G06F9/4418 ,  G06F13/4022 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D50/20

    摘要： System and method embodiments are provided for messaging-based System-on-a-chip (SoC) power gating. The embodiments enable fine granularity SoC power gating without introducing significant latency and substantially maximizes SoC power reduction. In an embodiment, a method in a first SoC resource for messaging-based power gating includes receiving at the first SoC resource a wakeup notification message (WNM) from a second SoC resource, wherein the WNM comprises a time at which a result message from the second SoC resource is expected to arrive at the first SoC resource; determining with the first SoC resource a wake-up time according to the time at which the result message from the second SoC resource is expected to arrive at the first SoC resource; setting a wake-up time timer to expire at the wake-up time; and waking up the first SoC resource when the wake-up time timer expires when the first SoC resource is asleep.

    摘要翻译： 为基于消息传递的片上系统（SoC）电源门控提供系统和方法实施例。 这些实施例使得细粒度SoC功率门控不引入显着的延迟并且基本上使SoC功率降低最大化。 在一个实施例中，用于基于消息的功率门控的第一SoC资源中的方法包括在第一SoC资源处从第二SoC资源接收唤醒通知消息（WNM），其中WNM包括来自 第二个SoC资源有望到达第一个SoC资源; 根据预期来自第二SoC资源的结果消息到达第一SoC资源的时间，利用第一SoC资源确定唤醒时间; 设置唤醒时间计时器在唤醒时间到期; 当第一个SoC资源处于睡眠状态时唤醒时间定时器到期时，唤醒第一个SoC资源。

    Memory system minimizing occurrences of storing of operation data in non-volatile storage during power saving mode
    67.
    发明授权
    Memory system minimizing occurrences of storing of operation data in non-volatile storage during power saving mode 有权
    存储系统最大限度地减少在省电模式下在非易失性存储器中存储操作数据的情况

    公开(公告)号：US09442560B2

    公开(公告)日：2016-09-13

    申请号：US14302835

    申请日：2014-06-12

    申请人： Kabushiki Kaisha Toshiba

    发明人： Shohei Asami ,  Toshikatsu Hida ,  Mitsunori Tadokoro ,  Hirokazu Morita

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3287 ,  G06F1/3268 ,  G06F1/3275 ,  G06F1/3293 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

    摘要： According to one embodiment, a memory system includes a non-volatile first storage unit, a second storage unit, a third storage unit, and a controller. The controller is configured to selectively execute, following transition to a first mode, either a procedure of writing data of the second storage unit in the third storage unit, or a procedure of writing data of the third storage unit in the first storage unit while reducing power feed to the first and third storage units.

    摘要翻译： 根据一个实施例，存储器系统包括非易失性第一存储单元，第二存储单元，第三存储单元和控制器。 控制器被配置为在转换到第一模式之后，选择性地执行将第二存储单元的数据写入第三存储单元的过程，或者将第三存储单元的数据写入第一存储单元的过程，同时减少 向第一和第三存储单元供电。

    Display co-processing
    68.
    发明授权
    Display co-processing 有权
    显示协同处理

    公开(公告)号：US09436970B2

    公开(公告)日：2016-09-06

    申请号：US14200213

    申请日：2014-03-07

    申请人： Google Technology Holdings LLC

    发明人： Nathan M. Connell ,  Christian L. Flowers ,  John W. Kaehler ,  George B. Standish

    IPC分类号： G06T1/20 ,  G06F3/14 ,  G06F1/32 ,  G06F9/50 ,  G09G5/00 ,  G09G5/36

    CPC分类号： G06T1/20 ,  G06F1/3293 ,  G06F3/14 ,  G06F3/1415 ,  G06F9/5044 ,  G09G5/005 ,  G09G5/006 ,  G09G5/363 ,  G09G2310/04 ,  G09G2320/0673 ,  G09G2330/021 ,  G09G2340/12 ,  G09G2360/06 ,  G09G2360/18 ,  G09G2370/10 ,  G09G2370/20 ,  Y02D10/122 ,  Y02D10/22 ,  Y02D50/20

    摘要： In embodiments of display co-processing, a computing device includes a display, a full-power processor, and a low-power processor that can alter visual content presented by the display without utilizing the full-power processor. The low-power processor can, responsive to a request from the full-power processor, generate additional display data to update display data stored in a frame-buffer of the display. The low-power processor can then transmit the additional display data to the frame-buffer effective to alter at least a portion of the visual content presented by the display. In some embodiments, the additional display data is transmitted via a protocol converter that forwards the display data to the display using a display-specific communication protocol.

    摘要翻译： 在显示协同处理的实施例中，计算设备包括显示器，全功率处理器和低功率处理器，其可以改变由显示器呈现的视觉内容而不使用全功率处理器。 低功率处理器可以响应于来自全功率处理器的请求产生附加的显示数据以更新存储在显示器的帧缓冲器中的显示数据。 低功率处理器然后可以将附加的显示数据发送到帧缓冲器，以有效地改变由显示器呈现的视觉内容的至少一部分。 在一些实施例中，附加显示数据经由协议转换器发送，该协议转换器使用显示专用通信协议将显示数据转发到显示器。

    Power control system and power control method
    70.
    发明授权
    Power control system and power control method 有权
    电源控制系统和电源控制方式

    公开(公告)号：US09411402B2

    公开(公告)日：2016-08-09

    申请号：US14080310

    申请日：2013-11-14

    申请人： GIGA-BYTE TECHNOLOGY CO., LTD.

    发明人： Mou Ming Ma ,  Chun Kun Lan ,  Yih Neng Lin

    IPC分类号： G06F1/26 ,  G06F1/32 ,  G06F11/14

    CPC分类号： G06F1/3234 ,  G06F1/266 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F11/1417 ,  Y02D10/171

    摘要： A power control system and a power control method are provided. The power control system is adapted to a computer device. The computer device comprises an embedded controller and a power supply both coupled to each other. The power supply provides power to the embedded controller. The power control system comprises a device switch input terminal and a logic output terminal. The device switch input terminal receives a trigger signal from a component of the computer device to change a state of the computer system. The logic output terminal is coupled to the power supply and performs on-off control of the power supply to provide or stop power to the embedded controller when the switch input terminal receives the trigger signal.

    摘要翻译： 提供了功率控制系统和功率控制方法。 功率控制系统适用于计算机设备。 计算机设备包括彼此耦合的嵌入式控制器和电源。 电源为嵌入式控制器提供电源。 功率控制系统包括设备开关输入端子和逻辑输出端子。 设备开关输入端子从计算机设备的组件接收触发信号以改变计算机系统的状态。 当开关输入端子接收到触发信号时，逻辑输出端子耦合到电源并执行电源的开关控制以向嵌入式控制器提供或停止电力。