公开(公告)号：US20140075105A1

公开(公告)日：2014-03-13

申请号：US14083163

申请日：2013-11-18

Applicant: PURE Storage, Inc.

Inventor： John Colgrove ,  John Hayes ,  Bo Hong ,  Feng Wang ,  Ethan Miller ,  Craig Harmer

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0629 ,  G06F3/0653 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0688 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/1076 ,  G06F11/3034 ,  G06F11/3055 ,  G06F11/3409 ,  G06F11/3485 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/262 ,  G06F2212/502

Abstract: A system and method for effectively scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The characteristics of corresponding storage devices are used to schedule I/O requests to the storage devices in order to maintain relatively consistent response times at predicted times. In order to reduce a likelihood of unscheduled behaviors of the storage devices, the storage controller is configured to schedule proactive operations on the storage devices that will reduce a number of occurrences of unscheduled behaviors.

Abstract translation: 一种用于在多个固态存储设备之间有效地调度读取和写入操作的系统和方法。 计算机系统包括经由网络彼此耦合的客户端计算机和数据存储阵列。 数据存储阵列利用固态驱动器和闪存单元进行数据存储。 数据存储阵列中的存储控制器包括I / O调度器。 相应的存储设备的特性用于将I / O请求调度到存储设备，以便在预测时间内保持相对一致的响应时间。 为了减少存储设备的非预定行为的可能性，存储控制器被配置为对存储设备上的主动操作进行调度，这将减少多个未排程行为的发生。

公开(公告)号：US20140059299A1

公开(公告)日：2014-02-27

申请号：US13595240

申请日：2012-08-27

Applicant: Suryanarayana Murthy Durbhakula ,  Yuan C. Chou

Inventor： Suryanarayana Murthy Durbhakula ,  Yuan C. Chou

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/502 ,  G06F2212/6026

Abstract: The disclosed embodiments relate to a method for dynamically changing a prefetching configuration in a computer system, wherein the prefetching configuration specifies how to change an ahead distance that specifies how many references ahead to prefetch for each stream. During operation of the computer system, the method keeps track of one or more stream lengths, wherein a stream is a sequence of memory references with a constant stride. Next, the method dynamically changes the prefetching configuration for the computer system based on observed stream lengths in a most-recent window of time.

Abstract translation: 所公开的实施例涉及用于在计算机系统中动态地改变预取配置的方法，其中预取配置指定如何改变预定距离，其指定在每个流之前预取多少个引用。 在计算机系统的操作期间，该方法跟踪一个或多个流长度，其中流是具有恒定步幅的存储器引用序列。 接下来，该方法基于在最近的时间窗口中观察到的流长度动态地改变计算机系统的预取配置。

公开(公告)号：US20140032873A1

公开(公告)日：2014-01-30

申请号：US13995469

申请日：2011-12-28

Applicant: Serkan Ozdemir ,  Qiong Cai ,  Ayose J. Falcon ,  Nevin Hyuseinova

Inventor： Serkan Ozdemir ,  Qiong Cai ,  Ayose J. Falcon ,  Nevin Hyuseinova

IPC: G06F12/06

CPC classification number: G06F12/06 ,  G06F12/0292 ,  G06F12/0646 ,  G06F13/16 ,  G06F2212/502 ,  G11C13/0004

Abstract: Embodiments of the invention describe an apparatus, system and method for workload adaptive address mapping. Embodiments of the invention may receive a request to initialize a system memory including a plurality of memory banks. Using a plurality of memory address mapping schemes for memory settings for the system memory, a system characterization workload is executed during the initialization of the system memory, the system characterization workload including a plurality of transactions directed towards the system memory. Embodiments of the invention may monitor target addresses of the plurality of transactions directed towards the system memory. One of the plurality of memory address mapping schemes is selected based, at least in part, on the target addresses of the plurality of transactions.

Abstract translation: 本发明的实施例描述了用于工作负载自适应地址映射的装置，系统和方法。 本发明的实施例可以接收初始化包括多个存储体的系统存储器的请求。 使用用于系统存储器的存储器设置的多个存储器地址映射方案，在系统存储器的初始化期间执行系统表征工作负载，系统表征工作负载包括指向系统存储器的多个事务。 本发明的实施例可以监视针对系统存储器的多个事务的目标地址。 至少部分地基于多个事务的目标地址来选择多个存储器地址映射方案中的一个。

公开(公告)号：US20140019677A1

公开(公告)日：2014-01-16

申请号：US13549819

申请日：2012-07-16

Applicant: Jichuan Chang ,  Parthasarathy Ranganathan

Inventor： Jichuan Chang ,  Parthasarathy Ranganathan

IPC: G06F12/08

CPC classification number: G06F3/0619 ,  G06F3/064 ,  G06F3/0685 ,  G06F3/0688 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/0895 ,  G06F12/121 ,  G06F2212/502 ,  Y02D10/13

Abstract: Storing data in persistent hybrid memory includes promoting a memory block from non-volatile memory to a cache based on a usage of said memory block according to a promotion policy, tracking modifications to the memory block while in the cache, and writing the memory block back into the non-volatile memory after the memory block is modified in the cache based on a writing policy that keeps a number of the memory blocks that are modified at or below a number threshold while maintaining the memory block in the cache.

Abstract translation: 将数据存储在永久性混合存储器中包括根据促销策略，基于所述存储器块的使用，将存储器块从非易失性存储器升级到高速缓存，在高速缓存中跟踪对存储器块的修改以及将存储器块写回 基于写入策略，在高速缓存中修改存储器块之后，在将存储器块保持在高速缓存中的同时保持修改数量或低于数字阈值的存储器块数量的情况下，进入非易失性存储器。

公开(公告)号：US08621156B1

公开(公告)日：2013-12-31

申请号：US13416109

申请日：2012-03-09

Applicant: Robert Cypher

Inventor： Robert Cypher

IPC: G06F12/00

CPC classification number: G06F12/0893 ,  G06F2212/1021 ,  G06F2212/502

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for labeled caching techniques. In one aspect, a method includes placing a plurality of items into a cache, each item having a label based on metadata associated with the item. A number of accesses are performed to respective items in the cache. A per-label stack distance histogram is determined for each label, including, for each label, determining a plurality of stack distances for accesses to items having the label. The cache is adjusted using the per-label stack distance histograms.

Abstract translation: 方法，系统和装置，包括在计算机存储介质上编码的计算机程序，用于标记的缓存技术。 一方面，一种方法包括将多个项目放置在高速缓存中，每个项目具有基于与该项目相关联的元数据的标签。 对高速缓存中的各个项目执行多个访问。 对于每个标签确定每个标签堆栈距离直方图，包括对于每个标签，确定用于对具有该标签的物品的访问的多个堆叠距离。 使用每标签堆栈距离直方图调整缓存。

公开(公告)号：US20130185511A1

公开(公告)日：2013-07-18

申请号：US13470643

申请日：2012-05-14

Applicant: Peter G. Sassone ,  Christopher Edward Koob ,  Dana M. Vantrease ,  Suresh K. Venkumahanti ,  Lucian Codrescu

Inventor： Peter G. Sassone ,  Christopher Edward Koob ,  Dana M. Vantrease ,  Suresh K. Venkumahanti ,  Lucian Codrescu

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F1/3275 ,  G06F1/3287 ,  G06F12/0806 ,  G06F12/0846 ,  G06F2212/1028 ,  G06F2212/502 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

Abstract: Embodiments disclosed in the detailed description include hybrid write-through/write-back cache policy managers, and related systems and methods. A cache write policy manager is configured to determine whether at least two caches among a plurality of parallel caches are active. If all of one or more other caches are not active, the cache write policy manager is configured to instruct an active cache among the parallel caches to apply a write-hack cache policy. In this manner, the cache write policy manager may conserve power and/or increase performance of a singly active processor core. If any of the one or more other caches are active, the cache write policy manager is configured to instruct an active cache among the parallel caches to apply a write-through cache policy. In this manner, the cache write policy manager facilitates data coherency among the parallel caches when multiple processor cores are active.

Abstract translation: 在详细描述中公开的实施例包括混合写入/回写高速缓存策略管理器以及相关的系统和方法。 高速缓存写策略管理器被配置为确定多个并行高速缓存中的至少两个高速缓存是否是活动的。 如果所有一个或多个其他高速缓存都不活动，则缓存写策略管理器被配置为指示并行高速缓存中的活动高速缓存来应用写入黑客缓存策略。 以这种方式，缓存写入策略管理器可以节省单个活动处理器核心的功率和/或提高性能。 如果一个或多个其他高速缓存中的任一个是活动的，则高速缓存写策略管理器被配置为指示并行高速缓存中的活动高速缓存来应用直写高速缓存策略。 以这种方式，当多个处理器核心处于活动状态时，缓存写入策略管理器便于并行高速缓存之间的数据一致性。

公开(公告)号：US08438338B2

公开(公告)日：2013-05-07

申请号：US12856682

申请日：2010-08-15

Applicant: Diane Garza Flemming ,  William A. Maron ,  Ram Raghavan ,  Mysore Sathyanarayana Srinivas ,  Basu Vaidyanathan

Inventor： Diane Garza Flemming ,  William A. Maron ,  Ram Raghavan ,  Mysore Sathyanarayana Srinivas ,  Basu Vaidyanathan

IPC: G06F12/02

CPC classification number: G06F12/0811 ,  G06F12/0284 ,  G06F2212/502 ,  G06F2212/604

Abstract: An approach is provided to identifying cache extension sizes that correspond to different partitions that are running on a computer system. The approach extends a first hardware cache associated with a first processing core that is included in the processor's silicon substrate with a first memory allocation from a system memory area, with the system memory area being external to the silicon substrate and the first memory allocation corresponding to one of the plurality of cache extension sizes that corresponds to one of the partitions that is running on the computer system. The approach further extends a second hardware cache associated with a second processing core also included in the processor's silicon substrate with a second memory allocation from the system memory area with the second memory allocation corresponding to another of the cache extension sizes that corresponds to a different partitions that is being executed by the second processing core.

Abstract translation: 提供了一种方法来识别对应于在计算机系统上运行的不同分区的高速缓存扩展大小。 该方法利用来自系统存储器区域的第一存储器分配来扩展与包括在处理器的硅衬底中的第一处理核心相关联的第一硬件高速缓存，系统存储器区域在硅衬底外部，并且第一存储器分配对应于 多个缓存扩展大小中的一个对应于在计算机系统上运行的分区之一。 该方法进一步扩展与第二处理核心相关联的第二硬件高速缓存，该第二处理核心还包括在处理器的硅衬底中，具有来自系统存储区域的第二存储器分配，其中第二存储器分配对应于对应于不同分区的另一个高速缓存扩展大小 正在由第二处理核心执行。

公开(公告)号：US20130111147A1

公开(公告)日：2013-05-02

申请号：US13285735

申请日：2011-10-31

Applicant: Jeffrey Clifford Mogul ,  Naveen Muralimanohar ,  Mehul A. Shah ,  Eric A. Anderson

Inventor： Jeffrey Clifford Mogul ,  Naveen Muralimanohar ,  Mehul A. Shah ,  Eric A. Anderson

IPC: G06F12/02 ,  G06F12/10

CPC classification number: G06F12/0802 ,  G06F8/4442 ,  G06F12/1027 ,  G06F2212/502 ,  G06F2212/6024 ,  Y02D10/13

Abstract: Example methods, apparatus, and articles of manufacture to access memory are disclosed. A disclosed example method involves receiving at least one runtime characteristic associated with accesses to contents of a memory page and dynamically adjusting a memory fetch width for accessing the memory page based on the at least one runtime characteristic.

Abstract translation: 公开了用于访问存储器的示例性方法，装置和制品。 所公开的示例性方法包括接收与对存储器页面的内容的访问相关联的至少一个运行时特性，并且基于至少一个运行时特性动态地调整用于访问存储器页面的存储器提取宽度。

公开(公告)号：US08433852B2

公开(公告)日：2013-04-30

申请号：US12871164

申请日：2010-08-30

Applicant: Shiliang Hu ,  Youfeng Wu

Inventor： Shiliang Hu ,  Youfeng Wu

IPC: G06F12/00

CPC classification number: G06F12/0862 ,  G06F2212/1041 ,  G06F2212/502 ,  G06F2212/6024 ,  G06F2212/6026

Abstract: In one embodiment, the present invention includes a prefetching engine to detect when data access strides in a memory fall into a range, to compute a predicted next stride, to selectively prefetch a cache line using the predicted next stride, and to dynamically control prefetching. Other embodiments are also described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种预取引擎，用于检测存储器中的数据访问步进何时落入一个范围内，以计算预测的下一步，以使用预测的下一步来选择性地预取高速缓存行，并且动态地控制预取。 还描述和要求保护其他实施例。

公开(公告)号：US08234457B2

公开(公告)日：2012-07-31

申请号：US11480128

申请日：2006-06-30

Applicant: Clark E. Lubbers ,  Michael D. Walker ,  David P. DeCenzo

Inventor： Clark E. Lubbers ,  Michael D. Walker ,  David P. DeCenzo

IPC: G06F12/00 ,  G06F12/12

CPC classification number: G06F12/0804 ,  G06F12/0868 ,  G06F2212/262 ,  G06F2212/502

Abstract: Method and apparatus for flushing cached writeback data to a storage array. Sets of writeback data are accumulated in a cache memory in an array with a view toward maintaining a substantially uniform distribution of the data across different locations of the storage array. The arrayed sets of data are thereafter transferred from the cache memory to the storage array substantially at a rate at which additional sets of writeback data are provided to the cache memory by a host. Each set of writeback data preferably comprises a plurality of contiguous data blocks, and are preferably written (flushed) to the storage in conjunction with the operation of a separate access command within a selected proximity range of the data with respect to the storage array. A stripe data descriptor (SDD) is preferably maintained for each set of writeback data in the array.

Abstract translation: 将缓存的回写数据冲洗到存储阵列的方法和装置。 回写数据集合在阵列中的高速缓冲存储器中累积，以保持在存储阵列的不同位置上的数据的基本上均匀的分布。 然后，数组的数据组从高速缓冲存储器传输到存储阵列，基本上以主机将高速缓冲存储器的额外的回写数据集提供给速率。 每组回写数据优选地包括多个相邻的数据块，并且优选地与数据相对于存储阵列的选定的接近范围内的单独访问命令的操作一起写入（刷新）到存储器。 条带数据描述符（SDD）优选地针对阵列中的每组回写数据维持。