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    Analog-to-digital converter having reduced circuit area
    61.
    发明授权
    Analog-to-digital converter having reduced circuit area 失效
    具有减小的电路面积的模数转换器

    公开(公告)号：US5594444A

    公开(公告)日：1997-01-14

    申请号：US611085

    申请日：1996-03-05

    Applicant: Chikara Yamada

    Inventor： Chikara Yamada

    IPC: H03M1/20 ,  H03M1/36 ,  H03M1/14

    CPC classification number: H03M1/206 ,  H03M1/363 ,  H03M1/365

    Abstract: In an analog-to-digital converter, a plurality of divided output currents are produced by dividing at a predetermined ratio each of a plurality of comparison output currents that are produced for each reference potential, and an output voltage generated by each divided comparison output current is further divided by an output means into a plurality of output voltages. A combination of output voltages which are in reversed-phase, and the relationship of which in magnitude is reversed at an intermediate potential between first and second reference potentials, is selected from the plurality of output voltages produced by the above division. According to this construction, comparison outputs of an input analog signal with respect to arbitrary virtual potentials between the two reference potentials actually given can easily be obtained.

    Abstract translation: 在模拟数字转换器中，通过以预定比例对每个参考电位产生的多个比较输出电流和由每个分压比较输出电流产生的输出电压分别产生多个分压输出电流 进一步被输出装置划分为多个输出电压。 从通过上述划分产生的多个输出电压中选择处于反相的输出电压的组合以及其在第一和第二参考电位之间的中间电位处的幅度的关系。 根据该结构，可以容易地获得输入模拟信号相对于实际给出的两个参考电位之间的任意虚拟电位的比较输出。

    SAR ADC AND ELECTRONIC DEVICE
    63.
    发明公开
    SAR ADC AND ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20230208431A1

    公开(公告)日：2023-06-29

    申请号：US17844413

    申请日：2022-06-20

    Applicant: SILEAD Inc.

    Inventor： Jinling Zhou

    IPC: H03M1/46 ,  H03M1/20 ,  H03M1/36 ,  H03K19/17736 ,  H03K19/20

    CPC classification number: H03M1/462 ,  H03M1/206 ,  H03M1/361 ,  H03K19/1774 ,  H03K19/20

    Abstract: A SAR ADC and an electronic device are disclosed. The SAR ADC includes a read clock generation circuit, configured to connect to a first output terminal and a second output terminal of a dynamic comparator, and generate a read clock signal for reading a first or a second comparison result based on the first and the second comparison result received from the dynamic comparator. The invention reads the comparison result using the read clock signal generated by grabbing the output of the comparator, and can improve the overall analog-to-digital conversion speed of the SAR ADC. Further, the present invention can detect the occurrence of metastable state of the comparator by judging that the output of the comparator has no pulse, and read the comparison result based on the backup clock generated by the operating clock of the comparator.

    FLASH ADC WITH INTERPOLATORS
    64.
    发明申请
    FLASH ADC WITH INTERPOLATORS 有权
    带插补器的闪存ADC

    公开(公告)号：US20160134298A1

    公开(公告)日：2016-05-12

    申请号：US14538013

    申请日：2014-11-11

    Applicant: MediaTek Inc.

    Inventor： Wen-Hua CHANG

    IPC: H03M1/20 ,  H03M1/36

    CPC classification number: H03M1/205 ,  H03M1/206 ,  H03M1/361 ,  H03M1/365

    Abstract: An ADC is provided. The ADC includes a plurality of pre-amplifiers, dynamic comparators coupled to the pre-amplifiers, interpolators and an encoder. Each pre-amplifier provides a pair of differential outputs according to a pair of differential analog signals and a first reference voltage and a second reference voltage different from the first reference voltage. Each dynamic comparator provides a first comparing signal and a second comparing signal according to the pair of differential outputs of the corresponding pre-amplifier. Each interpolator provides an interpolating signal according to the first and second comparing signals of two of the dynamic comparators. The encoder provides a digital output according to the interpolating signals. The first and second comparing signals are the same in a reset phase, and the first and second comparing signals are complementary according to the pair of differential outputs of the corresponding pre-amplifier in an evaluation phase.

    Abstract translation: 提供了一个ADC。 ADC包括多个预放大器，耦合到前置放大器，内插器和编码器的动态比较器。 每个前置放大器根据一对差分模拟信号和不同于第一参考电压的第一参考电压和第二参考电压提供一对差分输出。 每个动态比较器根据相应的前置放大器的差分输出对提供第一比较信号和第二比较信号。 每个内插器根据两个动态比较器的第一和第二比较信号提供内插信号。 编码器根据内插信号提供数字输出。 第一和第二比较信号在复位阶段相同，并且第一和第二比较信号根据评估阶段中对应的前置放大器的差分输出的对而互补。

    Comparison circuits
    65.
    发明授权
    Comparison circuits 有权

    公开(公告)号：US08514121B1

    公开(公告)日：2013-08-20

    申请号：US13430464

    申请日：2012-03-26

    Applicant: Yun-Shiang Shu

    Inventor： Yun-Shiang Shu

    IPC: H03M1/12

    CPC classification number: H03M1/50 ,  H03M1/00 ,  H03M1/12 ,  H03M1/206 ,  H03M1/365 ,  H03M2201/4233

    Abstract: A comparison circuit is provided and includes first and second comparators and a first time-to-digital comparator. The first comparator with a first offset voltage receives an input signal and generates a first comparison signal and a first inverse comparison signal. The second comparator receives the input signal and generates a second comparison signal and a second inverse comparison signal. The first offset voltage is larger than the second offset voltage. The first time-to-digital comparator receives the first comparison signal and the second inverse comparison signal and generates first and second determination signals according to the first comparison signal and the second inverse comparison signal. The first and second determination signals indicate whether a voltage of the input signal is larger than a first middle voltage. The first middle voltage is equal to a half of the sum of the first offset voltage and the second offset voltage.

    High resolution optical encoder systems having a set of light detecting elements each comprising a pair of complementary detectors (as amended)
    66.
    发明授权
    High resolution optical encoder systems having a set of light detecting elements each comprising a pair of complementary detectors (as amended) 失效
    具有一组光检测元件的高分辨率光学编码器系统，每个光检测元件包括一对互补检测器（经修改）

    公开(公告)号：US08188420B2

    公开(公告)日：2012-05-29

    申请号：US12618710

    申请日：2009-11-14

    Applicant: Wei Yan Lee

    Inventor： Wei Yan Lee

    IPC: G01D5/34

    CPC classification number: H03M1/206 ,  H03M1/303

    Abstract: Disclosed are various embodiments of front-end analog circuitry for use in conjunction with optical encoders. Highly accurate analog output signals are provided by front-end analog circuitry in incremental or absolute motion encoders to interpolation circuitry, which is capable of providing high interpolation factor output signals having high timing accuracy. The disclosed interpolation circuits may be implemented using CMOS or BiCMOS processes without undue effort.

    Abstract translation: 公开了与光学编码器一起使用的前端模拟电路的各种实施例。 高精度模拟输出信号由增量式或绝对运动编码器的前端模拟电路提供给插值电路，能够提供具有高定时精度的高内插因子输出信号。 公开的内插电路可以使用CMOS或BiCMOS处理而不用过度的努力来实现。

    UNFOLDING VCO-BASED QUANTIZATION CIRCUIT
    68.
    发明申请
    UNFOLDING VCO-BASED QUANTIZATION CIRCUIT 有权
    基于VCO的定量电路

    公开(公告)号：US20110025541A1

    公开(公告)日：2011-02-03

    申请号：US12512576

    申请日：2009-07-30

    Applicant: Christopher G. Guenther

    Inventor： Christopher G. Guenther

    IPC: H03M1/12 ,  H03M1/00

    CPC classification number: H03M1/206 ,  H03M1/60

    Abstract: Apparatus and methods are provided for a voltage-controlled oscillator (VCO) quantization circuit. A quantization circuit comprises an input node for an input signal, a VCO quantizer coupled to the input node, and an output generation module coupled to the VCO quantizer. The VCO quantizer is configured to generate a digital code that is representative of the input signal, wherein the digital code has a first code range. The output generation module generates a digital output value based on the digital code, wherein the digital output value has a second code range being greater than the first code range.

    Abstract translation: 为压控振荡器（VCO）量化电路提供了装置和方法。 量化电路包括用于输入信号的输入节点，耦合到输入节点的VCO量化器以及耦合到VCO量化器的输出产生模块。 VCO量化器被配置为产生代表输入信号的数字代码，其中数字代码具有第一代码范围。 输出产生模块基于数字代码产生数字输出值，其中数字输出值具有大于第一代码范围的第二代码范围。

    DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTER
    69.
    发明申请
    DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTER 有权
    DELTA-SIGMA模拟到数字转换器

    公开(公告)号：US20100066577A1

    公开(公告)日：2010-03-18

    申请号：US12485924

    申请日：2009-06-17

    Applicant: Sheng-Jui Huang

    Inventor： Sheng-Jui Huang

    IPC: H03M3/00

    CPC classification number: H03F3/45475 ,  H03F1/0277 ,  H03F3/211 ,  H03F3/45179 ,  H03F3/4565 ,  H03F3/45932 ,  H03F2200/408 ,  H03F2203/45366 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45514 ,  H03F2203/45562 ,  H03F2203/45594 ,  H03F2203/45644 ,  H03H11/1252 ,  H03H11/1291 ,  H03M1/0663 ,  H03M1/0809 ,  H03M1/206 ,  H03M1/361 ,  H03M1/806 ,  H03M3/424 ,  H03M3/448 ,  H03M3/464

    Abstract: An exemplary continuous-time delta-sigma analog-to-digital converter includes a loop filter, a quantizer, a dynamic element matching circuit, a latch, and a digital-to-analog converter (DAC). The loop filter contains a plurality of integrators coupled in series, including a first integrator and a second integrator; a first positive feedback resistive element, placed in a first positive feedback path between a first output node of the second integrator and a first input node of the first integrator; and a first negative feedback resistive element, placed in a first negative feedback path between a second output node of the second integrator and the first second input node of the first integrator. The quantizer is implemented using a domino quantizer. The DAC contains a plurality of DAC units each having a capacitive device, a resistive device, and a switch device coupled between the capacitive device and the resistive device.

    Abstract translation: 示例性连续时间Δ-Σ模数转换器包括环路滤波器，量化器，动态元件匹配电路，锁存器和数模转换器（DAC）。 环路滤波器包括串联耦合的多个积分器，包括第一积分器和第二积分器; 第一正反馈电阻元件，放置在第二积分器的第一输出节点与第一积分器的第一输入节点之间的第一正反馈路径中; 以及第一负反馈电阻元件，放置在第二积分器的第二输出节点与第一积分器的第一第二输入节点之间的第一负反馈路径中。 量化器使用多米诺量化器实现。 DAC包含多个DAC单元，每个DAC单元均具有电容性器件，电阻器件和耦合在电容器件和电阻器件之间的开关器件。

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