公开(公告)号：US11720719B2

公开(公告)日：2023-08-08

申请号：US16589989

申请日：2019-10-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chikara Kondo ,  Kazuhiro Kurihara

IPC: G06F21/85 ,  G06F21/79 ,  G11C29/12 ,  G06F12/14 ,  G06F21/60

CPC classification number: G06F21/85 ,  G06F12/1408 ,  G06F21/602 ,  G06F21/79 ,  G11C29/1201

Abstract: Apparatuses, systems, and methods for signal encryption in high bandwidth memory are described. A high bandwidth memory (HBM) may include a mix of secure circuits and non-secure circuits, which are coupled to secure and non-secure registers respectively. Information may be communicated between the secure and non-secure registers along an interface. The information associated with the secure register may be encrypted. When information is written to the secure register, an encryption circuit in the HBM may first decrypt the information before it is written to the secure register. When information is read from the secure register, it may first be encrypted by the encryption circuit before it is provided along the interface.

公开(公告)号：US11720495B2

公开(公告)日：2023-08-08

申请号：US16882380

申请日：2020-05-22

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Naveen Bhoria

IPC: G06F12/0811 ,  G06F9/46 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/1081 ,  G06F12/14 ,  G06F21/79 ,  G06F12/128 ,  G06F12/0864

CPC classification number: G06F12/0811 ,  G06F9/467 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/1081 ,  G06F12/1441 ,  G06F21/79

Abstract: In described examples, a coherent memory system includes a central processing unit (CPU) and first and second level caches. The CPU is arranged to execute program instructions to manipulate data in at least a first or second secure context. Each of the first and second caches stores a secure code for indicating the at least first or second secure contexts by which data for a respective cache line is received. The first and second level caches maintain coherency in response to comparing the secure codes of respective lines of cache and executing a cache coherency operation in response.

公开(公告)号：US20230229760A1

公开(公告)日：2023-07-20

申请号：US18188802

申请日：2023-03-23

Applicant: Osom Products, Inc.

Inventor： Jason Sean Gagne-Keats ,  Wolfgang Wesley Muller ,  Gary Anderson ,  Nicholas Franco ,  Jean-Baptiste Charles Theou

IPC: G06F21/54 ,  G06F21/53 ,  G06F21/60 ,  G06F21/79 ,  G06F21/57 ,  H04W12/37 ,  G06F9/4401 ,  G06F21/32 ,  G06F21/51 ,  G06F21/74

CPC classification number: G06F21/54 ,  G06F9/441 ,  G06F21/32 ,  G06F21/51 ,  G06F21/53 ,  G06F21/74 ,  G06F21/79 ,  G06F21/572 ,  G06F21/602 ,  H04W12/37 ,  G06F2221/2105 ,  G06F2221/2141

Abstract: A mobile device can detect an idle state and, in response, initiate an access monitoring function to covertly monitor activity involving a human interaction with the mobile device. The covert monitoring is undetectable by a user of the mobile device. The mobile device can then detect a human interaction with the mobile device and, in response, cause the mobile device to covertly capture and log one or more human interactions with the mobile device. An authorized user of the mobile device is enabled to review the log of human interactions with the mobile device.

公开(公告)号：US11704255B2

公开(公告)日：2023-07-18

申请号：US17530461

申请日：2021-11-19

Applicant: Micron Technology, Inc.

Inventor： Nathaniel J. Meier ,  Brenton P. Van Leeuwen

IPC: G06F12/14 ,  G06F3/06 ,  G06F21/62 ,  H04L9/32 ,  G11C11/4074 ,  G11C17/16 ,  G06F21/79

CPC classification number: G06F12/1433 ,  G06F12/1466 ,  G06F21/79 ,  G11C11/4074 ,  G11C17/16 ,  G06F3/0622 ,  G06F3/0637 ,  G06F12/14 ,  G06F12/1458 ,  G06F2212/1052

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which security measures may be implemented to control access to a fuse array (or other secure features) of the memory devices based on a secure access key. In some cases, a customer may define and store a user-defined access key in the fuse array. In other cases, a manufacturer of the memory device may define a manufacturer-defined access key (e.g., an access key based on fuse identification (FID), a secret access key), where a host device coupled with the memory device may obtain the manufacturer-defined access key according to certain protocols. The memory device may compare an access key included in a command directed to the memory device with either the user-defined access key or the manufacturer-defined access key to determine whether to permit or prohibit execution of the command based on the comparison.

公开(公告)号：US20230216848A1

公开(公告)日：2023-07-06

申请号：US18181432

申请日：2023-03-09

Applicant: Google LLC

Inventor： Benjamin C. Serebrin

IPC: H04L9/40 ,  G06F12/14 ,  G06F21/79 ,  G06F12/1081 ,  H04L9/32

CPC classification number: H04L63/0876 ,  G06F12/1475 ,  G06F21/79 ,  G06F12/1081 ,  G06F12/1408 ,  H04L9/3247 ,  H04L63/062 ,  H04L63/164 ,  G06F2212/1052

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating signed addresses. One of the methods includes receiving, by a component from a device, a plurality of first requests, each first request for a physical address and including a virtual address, determining, by the component, a first physical address using the virtual address, generating a first signature for the first physical address, and providing, to the device, a response that includes the first signature, receiving, from the device, a plurality of second requests, each second request for access to a second physical address and including a second signature, determining, by the component for each of the plurality of second requests, whether the second physical address is valid using the second signature, and for each second request for which the second physical address is determined to be valid, servicing the corresponding second request.

公开(公告)号：US11693052B2

公开(公告)日：2023-07-04

申请号：US17722361

申请日：2022-04-17

Applicant: SiliconAid Solutions, Inc.

Inventor： James M. Johnson ,  Alfred L. Crouch

IPC: G01R31/317 ,  G01R31/3185 ,  G06F21/79 ,  H04L9/08

CPC classification number: G01R31/31719 ,  G01R31/318588 ,  G06F21/79 ,  H04L9/0861 ,  H04L2209/12

Abstract: A network of storage units has a data path, which is at least a portion of the network. The network also has a dynamic time-varying or cycle-varying code generation unit and a code comparator unit that together make up an unlock signal generation unit; and a gateway storage unit. If the gateway storage unit does not store an unlock signal or the unlock signal generation unit does not generate and transmit an unlock signal, the gateway storage unit does not insert a data path segment in the data path. If the unlock signal generation unit is operated such that it generates an unlock signal, and it transmits that unlock signal to a gateway storage unit, and the gateway storage unit stores the unlock signal value, then the gateway storage unit inserts a data path segment into the data path.

公开(公告)号：US11681636B2

公开(公告)日：2023-06-20

申请号：US16981816

申请日：2019-02-12

Applicant: Arm Limited

Inventor： Graeme Peter Barnes ,  Jasen Milov Borisov

IPC: G06F12/14 ,  G06F7/58 ,  G06F9/30 ,  G06F21/79 ,  G06F12/0842 ,  G06F12/0853 ,  G06F12/0897 ,  G06F12/1027

CPC classification number: G06F12/1441 ,  G06F7/582 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/30145 ,  G06F12/0842 ,  G06F12/0853 ,  G06F12/0897 ,  G06F12/1027 ,  G06F21/79

Abstract: An apparatus has processing circuitry (4); memory access circuitry (15) to perform a guard tag check for a tag checking target address having an associated address tag, the guard tag check comprising comparing the address tag with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address; and an instruction decoder (6) responsive to a random tag setting instruction specifying a tag setting target address, to control the processing circuitry (4) to set the address tag associated with the tag setting target address to a random tag value randomly selected from a set of candidate tag values.

公开(公告)号：US20230185732A1

公开(公告)日：2023-06-15

申请号：US18107399

申请日：2023-02-08

Applicant: Intel Corporation

Inventor： Weigang Li ,  Changzheng Wei ,  John Barry ,  Maryam Tahhan ,  Jonas Alexander Svennebring ,  Niall D. McDonnell ,  Alexander Leckey ,  Patrick Fleming ,  Christopher MacNamara ,  John Joseph Browne

IPC: G06F12/14 ,  G06F13/16 ,  G06F13/28 ,  G06F21/53 ,  G06F21/60 ,  G06F21/79

CPC classification number: G06F12/1408 ,  G06F13/1668 ,  G06F13/28 ,  G06F21/53 ,  G06F21/602 ,  G06F21/606 ,  G06F21/79 ,  G06F2213/0038

Abstract: There is disclosed a computing apparatus, including: a memory; a memory encryption controller to encrypt at least a region of the memory; and a network interface to communicatively couple the computing apparatus to a remote host; wherein the memory encryption controller is configured to send an encrypted packet decryptable via an encryption key directly from the memory to the remote host via the network interface, bypassing a network protocol stack.

公开(公告)号：US11669644B2

公开(公告)日：2023-06-06

申请号：US17031157

申请日：2020-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongwook Kim

IPC: G06F21/00 ,  G06F21/79 ,  G06F21/60 ,  G11C29/42 ,  G06F13/40 ,  G06F21/64

CPC classification number: G06F21/79 ,  G06F13/409 ,  G06F13/4068 ,  G06F21/602 ,  G06F21/64 ,  G11C29/42

Abstract: A storage device includes a non-volatile memory device, a memory controller, a secure element, and a wireless power received. The memory controller encrypts data using key information and stores the encrypted data in the non-volatile memory device, or reads the encrypted data from the non-volatile memory device, decrypts the read encrypted data using the key information, and outputs the decrypted data to an external device. The secure element stores the key information. The wireless power receiver, when the key information of the secure element is destroyed, receives wireless power from an external wireless device and provides the wireless power to the secure element.

公开(公告)号：US11669625B2

公开(公告)日：2023-06-06

申请号：US17134405

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： David M. Durham ,  Karanvir S. Grewal ,  Michael D. LeMay ,  Salmin Sultana

IPC: G06F21/60 ,  G06F21/79 ,  G06F9/50 ,  G06F9/30 ,  G06F21/54

CPC classification number: G06F21/602 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/5016 ,  G06F21/54 ,  G06F21/79

Abstract: A processor includes a register to store an encoded pointer to a memory location in memory and the encoded pointer is to include an encrypted portion. The processor further includes circuitry to determine a first data encryption factor based on a first data access instruction, decode the encoded pointer to obtain a memory address of the memory location, use the memory address to access an encrypted first data element, and decrypt the encrypted first data element using a cryptographic algorithm with first inputs to generate a decrypted first data element. The first inputs include the first data encryption factor based on the first data access instruction and a second data encryption factor from the encoded pointer.