公开(公告)号：US20240096620A1

公开(公告)日：2024-03-21

申请号：US18466542

申请日：2023-09-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Bilel Saidi

IPC: H01L21/02 ,  H01L29/04

CPC classification number: H01L21/02667 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L29/04

Abstract: An embodiment provides a method of forming a semiconductor device. A first silicon layer is deposited in a trench of a semiconductor substrate as an amorphous layer. A second silicon layer is deposited on top of and in contact with the first silicon layer as a polysilicon layer. After depositing the second silicon layer, the first silicon layer includes polysilicon having an average grain size different than an average grain size of the second silicon layer. A third semiconductor layer is deposited on top of and in contact with the second silicon layer to at least partially fill the trench.

公开(公告)号：US20240081160A1

公开(公告)日：2024-03-07

申请号：US18506383

申请日：2023-11-10

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe BOIVIN ,  Simon JEANNOT

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/231 ,  H10B63/30 ,  H10B63/80 ,  H10N70/011 ,  H10N70/061 ,  H10N70/253 ,  H10N70/823 ,  H10N70/826 ,  H10N70/8265 ,  H10N70/8413 ,  H10N70/8828 ,  G11C13/0004

Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.

公开(公告)号：US20240079421A1

公开(公告)日：2024-03-07

申请号：US18186115

申请日：2023-03-17

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMicroelectronics (Crolles 2) SAS

Inventor： Axel CROCHERIE ,  Alain OSTROVSKY ,  Jerome VAILLANT ,  Francois DENEUVILLE

IPC: H01L27/146

CPC classification number: H01L27/14607 ,  H01L27/14603 ,  H01L27/14643

Abstract: The present description concerns an image sensor formed inside and on top of a semiconductor substrate, the sensor comprising a plurality of pixels, each comprising a photodetector formed in the substrate, the sensor comprising at least first and second bidimensional metasurfaces stacked, in this order, in front of said plurality of pixels, each metasurface being formed of a bidimensional array of pads, the first metasurface having a first optical function and the second metasurface having a second optical function different from the first optical function.

公开(公告)号：US11923465B2

公开(公告)日：2024-03-05

申请号：US17125654

申请日：2020-12-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Arnaud Tournier ,  Boris Rodrigues Goncalves ,  Frederic Lalanne

IPC: H01L31/02 ,  H01L27/146

CPC classification number: H01L31/02019 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/1463 ,  H01L31/02005 ,  H01L27/14643

Abstract: The present disclosure concerns a photodiode including at least one memory area, each memory area including at least two charge storage regions.

公开(公告)号：US20240063290A1

公开(公告)日：2024-02-22

申请号：US18383926

申请日：2023-10-26

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Alexis GAUTHIER ,  Pascal CHEVALIER

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/732

CPC classification number: H01L29/66272 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/732 ,  H01L21/26513

Abstract: A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.

公开(公告)号：US11901381B2

公开(公告)日：2024-02-13

申请号：US16925248

申请日：2020-07-09

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Andrej Suler

IPC: H01L27/146

CPC classification number: H01L27/14614 ,  H01L27/1464 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14645 ,  H01L27/14689

Abstract: The present disclosure concerns an image sensor including a plurality of pixels, each including: a doped photosensitive region of a first conductivity type extending vertically in a semiconductor substrate; a charge collection region more heavily doped with the first conductivity type than the photosensitive region, extending vertically in the substrate from an upper surface of the substrate and being arranged above the photosensitive region; and a vertical stack including a vertical transfer gate and a vertical electric insulation wall, the stack crossing the substrate and being in contact with the charge collection region, the gate being arranged on the upper surface side of the substrate and penetrating into the substrate deeper than the charge collection region.

公开(公告)号：US11901216B2

公开(公告)日：2024-02-13

申请号：US17496411

申请日：2021-10-07

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pascal Gouraud ,  Delia Ristoiu

IPC: H01L21/00 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L21/7621 ,  H01L29/0649

Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.

公开(公告)号：US20240014215A1

公开(公告)日：2024-01-11

申请号：US18343298

申请日：2023-06-28

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexandre Villaret ,  Olivier Weber ,  Franck Arnaud

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/84

CPC classification number: H01L27/1207 ,  H01L29/7838 ,  H01L21/84

Abstract: A method can be used for manufacturing a high-voltage transistor in and on a high-voltage region of a silicon-on-insulator type bulk that includes a semiconductor film having a first thickness, electrically insulated from a carrier bulk by a buried dielectric layer. The semiconductor film in the high-voltage region is selectively epitaxially grown to a second thickness that is greater than the first thickness while the semiconductor film remains at the first thickness in a region outside the high-voltage region.

公开(公告)号：US11869772B2

公开(公告)日：2024-01-09

申请号：US17338379

申请日：2021-06-03

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Denis Monnier ,  Olivier Gonnard

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/285

CPC classification number: H01L21/28052 ,  H01L21/2855 ,  H01L21/28079 ,  H01L21/823443

Abstract: A exemplary semiconductor device includes a first gate structure overlying a surface of the semiconductor body, the first gate structure being silicided. A second gate structure overlies the surface of the semiconductor body and not being silicided. An oxide layer overlies the second gate structure and extends toward the first gate structure. A silicon nitride region is laterally spaced from the second gate structure and overlies a portion of the oxide layer between the first gate structure and the second gate structure.

公开(公告)号：US20230411450A1

公开(公告)日：2023-12-21

申请号：US18330287

申请日：2023-06-06

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Remy BERTHELON ,  Olivier WEBER

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/321

CPC classification number: H01L29/0649 ,  H01L21/76229 ,  H01L21/3212 ,  H10B63/10

Abstract: The present description concerns a method of manufacturing a device comprising a first portion having an array of memory cells formed therein and a second portion having transistors formed therein, the method comprising: a. the forming of first insulating trenches separating from one another the substrate regions of a same cell row, and b. the forming of second trenches separating from one another the regions of a same cell column, the second trenches having a height greater than the height of the first trenches, step a. comprising the independent forming of a lower portion and of an upper portion of each first trench, the forming of the upper portions comprising the deposition of a first insulating layer, the etching of the portions of the first insulating layer which are not located on the upper portions.