公开(公告)号：US20160099696A1

公开(公告)日：2016-04-07

申请号：US14971359

申请日：2015-12-16

Applicant: STMicroelectronics, Inc.

Inventor： Davy Choi

IPC: H03G3/02 ,  H03F3/45

CPC classification number: H03G3/02 ,  H03F1/0205 ,  H03F1/26 ,  H03F3/3022 ,  H03F3/393 ,  H03F3/45 ,  H03F3/45094 ,  H03F3/45179 ,  H03F3/45475 ,  H03F2200/261 ,  H03F2203/45116 ,  H03F2203/45138 ,  H03F2203/45336 ,  H03G1/0035 ,  H03G1/02 ,  H03G3/3036 ,  H03M1/18

Abstract: An instrumentation amplifier includes first and second resistors for gain setting. The operational amplifiers within the instrumentation amplifier include selectively enabled current drive sources coupled to the amplifier output. The first and second resistors have variable resistances. A control circuit is configured to select the variable resistances of the first and second resistors to implement a fixed gain for the instrumentation amplifier and further selectively enable the current drive sources. The control circuit receives an indication of a downstream programmable gain (for example, from a downstream programmable gain amplifier). The variable resistances of the first and second resistors are selected to be scaled inversely with respect to the downstream programmable gain and the current drive sources are enabled proportionately with respect to the downstream programmable gain.

公开(公告)号：US09300952B2

公开(公告)日：2016-03-29

申请号：US14255357

申请日：2014-04-17

Applicant: STMicroelectronics, Inc.

Inventor： Greg Neal

IPC: H04N13/04

CPC classification number: H04N13/398 ,  H04N13/341 ,  H04N2213/008

Abstract: Methods and systems are described for enabling the operation of a stereoscopic viewing device such that the viewing device provides a movable viewing window that enables the 3D rendering of 3D image data displayed by a backlit LCD device. In a particular implementation, the systems and methods disclosed herein are operable to control the operation of a pair of LCD shutter glasses.

Abstract translation: 描述了用于使立体观看设备的操作的方法和系统，使得观看设备提供可启动由背光LCD设备显示的3D图像数据的3D渲染的可移动观看窗口。 在具体实施方案中，本文公开的系统和方法可操作以控制一对LCD快门眼镜的操作。

公开(公告)号：US09293474B2

公开(公告)日：2016-03-22

申请号：US14739736

申请日：2015-06-15

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc. ,  Commissariat A l'Energie atomique et aux Energies alternatives

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Qing Liu ,  Laurent Grenouillet ,  Yannick Le Tiec ,  Maud Vinet

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L21/02

CPC classification number: H01L27/1207 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/161

Abstract: Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal. Within each of the SOI region and the bulk region, two types of semiconductor material portions are formed depending on whether a semiconductor material intermixes with the semiconductor alloy material.

公开(公告)号：US09263343B2

公开(公告)日：2016-02-16

申请号：US14327343

申请日：2014-07-09

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Nicolas Loubet ,  Balasubramanian Pranatharthiharan

IPC: H01L21/8238 ,  H01L29/161 ,  H01L27/092 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/823814 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/161 ,  H01L29/6656

Abstract: Silicon germanium regions are formed adjacent gates electrodes over both n-type and p-type regions in an integrated circuit. A hard mask patterned by lithography then protects structures over the p-type region while the silicon germanium is selectively removed from over the n-type region, even under remnants of the hard mask on sidewall spacers on the gate electrode. Silicon germanium carbon is epitaxially grown adjacent the gate electrode in place of the removed silicon germanium, and source/drain extension implants are performed prior to removal of the remaining hard mask over the p-type region structures.

Abstract translation: 在集成电路中，在n型和p型区域上形成邻近栅电极的硅锗区。 通过光刻图案化的硬掩模即使在栅电极上的侧壁间隔物上的硬掩模的残留物上，也可以在p型区域上保护结构，同时从n型区域上选择性地除去硅锗。 锗栅极外延生长硅代替去除的硅锗，并且在去除p型区域结构之前的剩余硬掩模之前进行源极/漏极延伸植入。

公开(公告)号：US09257450B2

公开(公告)日：2016-02-09

申请号：US14182632

申请日：2014-02-18

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicolas Loubet ,  James Kuss

IPC: H01L29/16 ,  H01L27/12 ,  H01L21/84 ,  H01L29/165 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L27/1211 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/78696

Abstract: A method for making a semiconductor device may include forming, above a substrate, a stack of alternating layers of first and second semiconductor materials. The second semiconductor material may be different than the first semiconductor material. The method may further include forming fins from the stack, with each fin having alternating layers of the first and second semiconductor materials, and selectively removing sidewall portions of the second semiconductor material from the fins to define recesses therein. The method may also include forming a dielectric material within the recesses, forming additional first semiconductor material on sidewall portions of the first semiconductor material in the fins, and forming a dielectric layer overlying the fins to define nanowires including the first semiconductor material within the dielectric layer.

Abstract translation: 制造半导体器件的方法可以包括在衬底之上形成第一和第二半导体材料的交替层叠。 第二半导体材料可以不同于第一半导体材料。 该方法还可以包括从堆叠形成翅片，其中每个翅片具有第一和第二半导体材料的交替层，并且从翅片选择性地去除第二半导体材料的侧壁部分以在其中限定凹部。 该方法还可以包括在凹槽内形成介电材料，在鳍片中的第一半导体材料的侧壁部分上形成附加的第一半导体材料，以及形成覆盖鳍片的介电层，以限定纳米线，该纳米线包括介电层内的第一半导体材料 。

公开(公告)号：US09254510B2

公开(公告)日：2016-02-09

申请号：US13365401

申请日：2012-02-03

Applicant: John H. Zhang

Inventor： John H. Zhang

IPC: H01L21/67 ,  B08B1/04 ,  A46B13/02 ,  F26B21/00 ,  A46B13/00

CPC classification number: B08B1/04 ,  A46B13/001 ,  A46B13/02 ,  F26B21/00 ,  H01L21/67034 ,  H01L21/67046 ,  Y10T29/494 ,  Y10T137/8593

Abstract: A drying apparatus for drying a semiconductor wafer includes a processing chamber including a rinsing section and a drying section adjacent thereto. The rinsing section has a chamber loading slot associated therewith for receiving the semiconductor wafer. The drying section has a chamber unloading slot associated therewith for outputting the semiconductor wafer. An exhaust control cap is carried by the processing chamber and includes a bottom wall, a top wall, at least one intermediate wall between the bottom and top walls, and a side wall coupled to the top, bottom and the at least one intermediate wall to define stacked exhaust sections. The exhaust control cap has a cap loading slot aligned with the chamber loading slot, a cap unloading slot aligned with the chamber unloading slot, and at least one exhaust port configured to be coupled to a vacuum source.

Abstract translation: 用于干燥半导体晶片的干燥装置包括具有漂洗部和与其相邻的干燥部的处理室。 漂洗部分具有与其相关联的腔室装载槽，用于接收半导体晶片。 干燥部具有与其相关联的室卸载槽，用于输出半导体晶片。 排气控制帽由处理室承载，并且包括底壁，顶壁，底壁和顶壁之间的至少一个中间壁，以及耦合到顶壁，底部和至少一个中间壁的侧壁，至 定义堆叠排气段。 排气控制盖具有与室装载槽对准的盖装载槽，与室卸载槽对准的盖卸载槽以及配置成联接到真空源的至少一个排气口。

公开(公告)号：US20160035843A1

公开(公告)日：2016-02-04

申请号：US14782190

申请日：2013-04-03

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERIGES ALTERNATIVES ,  STMICROELECTRONICS INC

Inventor： Maud VINET ,  Laurent GRENOUILLET ,  Qing LIU

IPC: H01L29/417 ,  H01L21/311 ,  H01L29/06 ,  H01L21/32 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L29/41783 ,  H01L21/31133 ,  H01L21/32 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/6656

Abstract: A method for manufacturing a microelectronic device with transistors of different types having raised source and drain regions and different overlap regions.

Abstract translation: 一种用于制造具有不同类型的具有升高的源极和漏极区域以及不同重叠区域的晶体管的微电子器件的方法。

公开(公告)号：US20160035820A1

公开(公告)日：2016-02-04

申请号：US14447678

申请日：2014-07-31

Applicant: STMicroelectronics, Inc. ,  Commissariat a l'Energie Atomique et aux Energies Alternatives ,  GLOBALFOUNDRIES Inc.

Inventor： Pierre Morin ,  Maud Vinet ,  Laurent Grenouillet ,  Ajey Poovannummoottil Jacob

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0607 ,  H01L21/02636 ,  H01L21/283 ,  H01L21/3086 ,  H01L21/32 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/1066 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7847 ,  H01L29/7849

Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.

公开(公告)号：US09246458B2

公开(公告)日：2016-01-26

申请号：US14296914

申请日：2014-06-05

Applicant: STMicroelectronics, Inc.

Inventor： Davy Choi

IPC: H03G1/00 ,  H03F3/45 ,  H03F1/02

CPC classification number: H03G3/02 ,  H03F1/0205 ,  H03F1/26 ,  H03F3/3022 ,  H03F3/393 ,  H03F3/45 ,  H03F3/45094 ,  H03F3/45179 ,  H03F3/45475 ,  H03F2200/261 ,  H03F2203/45116 ,  H03F2203/45138 ,  H03F2203/45336 ,  H03G1/0035 ,  H03G1/02 ,  H03G3/3036 ,  H03M1/18

Abstract: An instrumentation amplifier includes first and second resistors for gain setting. The operational amplifiers within the instrumentation amplifier include selectively enabled current drive sources coupled to the amplifier output. The first and second resistors have variable resistances. A control circuit is configured to select the variable resistances of the first and second resistors to implement a fixed gain for the instrumentation amplifier and further selectively enable the current drive sources. The control circuit receives an indication of a downstream programmable gain (for example, from a downstream programmable gain amplifier). The variable resistances of the first and second resistors are selected to be scaled inversely with respect to the downstream programmable gain and the current drive sources are enabled proportionately with respect to the downstream programmable gain.

Abstract translation: 仪表放大器包括用于增益设定的第一和第二电阻器。 仪表放大器内的运算放大器包括耦合到放大器输出的有选择地使能的电流驱动源。 第一和第二电阻具有可变电阻。 控制电路被配置为选择第一和第二电阻器的可变电阻以实现仪器放大器的固定增益，并且进一步选择性地启用当前的驱动源。 控制电路接收下游可编程增益的指示（例如，从下游可编程增益放大器）。 第一和第二电阻器的可变电阻被选择为相对于下游可编程增益反相缩放，并且当前驱动源相对于下游可编程增益成比例地启用。

公开(公告)号：US09244236B2

公开(公告)日：2016-01-26

申请号：US14802504

申请日：2015-07-17

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: G02B6/42 ,  G02B6/43 ,  G02B6/122 ,  G02B6/124 ,  G02B6/132 ,  G02B6/136 ,  G02B6/12

CPC classification number: G02B6/43 ,  G02B6/122 ,  G02B6/124 ,  G02B6/132 ,  G02B6/136 ,  G02B6/42 ,  G02B6/4214 ,  G02B2006/12102

Abstract: A photonic integrated circuit includes optical circuitry fabricated over an underlying circuitry layer. The optical circuitry includes a dielectric material having recesses disposed within, layers of a light waveguide material deposited within the recesses, and lenses disposed over each layer of waveguide material. The underlying circuitry layer may include, for example, a semiconductor wafer as well as circuitry fabricated during front end of line (FEOL) semiconductor manufacturing such as, for example, sources, gates, drains, interconnects, contacts, resistors, and other circuitry that may be manufactured during FEOL processes. The underlying circuitry layer may also include circuitry manufactured during back end of line semiconductor manufacturing processes such as, for example, interconnect structures, metallization layers, and contacts.

Abstract translation: 光子集成电路包括在底层电路层上制造的光电路。 光学电路包括具有设置在沉积在凹部内的光波导材料的层内的凹槽的介电材料和设置在每层波导材料上的透镜。 底层电路层可以包括例如半导体晶片以及在前端（FEOL）半导体制造期间制造的电路，例如源，栅极，漏极，互连，触点，电阻器和其他电路，其中 可以在FEOL过程中制造。 底层电路层还可以包括在线半导体制造工艺的后端制造的电路，例如互连结构，金属化层和触点。