公开(公告)号：US12021550B2

公开(公告)日：2024-06-25

申请号：US17119892

申请日：2020-12-11

Applicant: Intel Corporation

Inventor： Smita Kumar ,  Sailesh Bissessur ,  David K. Cassetti ,  Stephen T. Palermo

IPC: G06F16/00 ,  G06F16/22 ,  H03M7/30 ,  H03M7/40

CPC classification number: H03M7/3086 ,  G06F16/2255 ,  H03M7/40

Abstract: Examples described herein relate to an encoder circuitry to apply one of multiple lossless data compression schemes on input data. In some examples, to compress input data, the encoder circuitry is to utilize a search window size and number of searches based on an applied compression scheme. In some examples, content of a memory is reconfigured to store data corresponding to a search window size of the applied compression scheme. In some examples, an applicable hash function is configured based on the applied compression scheme. In some examples, a number of searches are made for a byte position. In some examples, the encoder circuitry includes a hash table look-up and a bank decoder. In some examples, the hash table look-up is to generate a hash index to identify an address of an entry in the search window. In some examples, the bank decoder is to select a bank based on the hash index.

公开(公告)号：US12020054B2

公开(公告)日：2024-06-25

申请号：US17256204

申请日：2018-11-30

Applicant: Intel Corporation

Inventor： Kun Tian ,  Ankur Shah ,  David Cowperthwaite ,  Zhi Wang ,  Zhenyu Wang ,  Kalyan Kondapally ,  Jonathan Bloomfield ,  Wei Zhang

IPC: G06F9/455 ,  G06F3/14 ,  G06F9/4401 ,  G06F9/451 ,  G09G5/00 ,  G09G5/393 ,  G09G5/395

CPC classification number: G06F9/45558 ,  G06F3/1407 ,  G06F9/4411 ,  G06F9/452 ,  G06F9/455 ,  G09G5/001 ,  G09G5/006 ,  G06F2009/45562 ,  G06F2009/45595 ,  G09G5/393 ,  G09G5/395

Abstract: Apparatus and method for implementing a virtual display. For example, one embodiment of a graphics processing apparatus comprises at least one configuration register to store framebuffer descriptor information for a first guest running on a first virtual machine (VM) in a virtualized execution environment of a host processor, the framebuffer descriptor information to indicate one or more display pipes assigned to the first guest; and execution circuitry to execute a first driver assigned to the first guest, the first guest to use the first driver to display a framebuffer in a plane associated with one of the display pipes in accordance with the framebuffer descriptor information.

公开(公告)号：US12020033B2

公开(公告)日：2024-06-25

申请号：US17133899

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Niranjan Kumar Soundararajan ,  Sreenivas Subramoney ,  Jayesh Gaur ,  S R Swamy Saranam Chongala

IPC: G06F9/38 ,  G06F9/22

CPC classification number: G06F9/3836 ,  G06F9/223 ,  G06F9/3838

Abstract: Apparatus and method for memorizing repeat function calls are described herein. An apparatus embodiment includes: uop buffer circuitry to identify a function for memorization based on retiring micro-operations (uops) from a processing pipeline; memorization retirement circuitry to generate a signature of the function which includes input and output data of the function; a memorization data structure to store the signature; and predictor circuitry to detect an instance of the function to be executed by the processing pipeline and to responsively exclude a first subset of uops associated with the instance from execution when a confidence level associated with the function is above a threshold. One or more instructions that are data-dependent on execution of the instance is then provided with the output data of the function from the memorization data structure.

公开(公告)号：US12020031B2

公开(公告)日：2024-06-25

申请号：US17334901

申请日：2021-05-31

Applicant: Intel Corporation

Inventor： Michael Mishaeli ,  Jason W. Brandt ,  Gilbert Neiger ,  Asit K. Mallick ,  Rajesh M. Sankaran ,  Raghunandan Makaram ,  Benjamin C. Chaffin ,  James B. Crossland ,  H. Peter Anvin

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F13/40

CPC classification number: G06F9/3009 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/3851 ,  G06F9/485 ,  G06F13/4068

Abstract: A processor of an aspect includes a decode unit to decode a user-level suspend thread instruction that is to indicate a first alternate state. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the instruction at a user privilege level. The execution unit in response to the instruction, is to: (a) suspend execution of a user-level thread, from which the instruction is to have been received; (b) transition a logical processor, on which the user-level thread was to have been running, to the indicated first alternate state; and (c) resume the execution of the user-level thread, when the logical processor is in the indicated first alternate state, with a latency that is to be less than half a latency that execution of a thread can be resumed when the logical processor is in a halt processor power state.

公开(公告)号：US12019733B2

公开(公告)日：2024-06-25

申请号：US17692464

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Michael LeMay

IPC: G06F21/52

CPC classification number: G06F21/52 ,  G06F2221/034

Abstract: A method comprises receiving, in a store buffer, at least a portion of a store instruction, the at least a portion of the store instruction comprising a data operand, receiving, a load instruction for execution; and determining whether the store instruction and the load instruction are in different compartments.

公开(公告)号：US12019562B2

公开(公告)日：2024-06-25

申请号：US17481405

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Michael D. LeMay ,  David M. Durham ,  Anjo Lucas Vahldiek-Oberwagner ,  Anna Trikalinou

IPC: G06F12/14 ,  G06F12/1027

CPC classification number: G06F12/1408 ,  G06F12/1027 ,  G06F12/1441 ,  G06F12/1466

Abstract: An apparatus comprising a processor unit comprising circuitry to generate, for a first network host, a request for an object of a second network host, wherein the request comprises an address comprising a routable host ID of the second network host and an at least partially encrypted object ID, wherein the address uniquely identifies the object within a distributed computing domain; and a memory element to store at least a portion of the object.

公开(公告)号：US20240206348A1

公开(公告)日：2024-06-20

申请号：US18083493

申请日：2022-12-17

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Chia-Ching Lin ,  Hai Li

IPC: H10N52/85 ,  G11C11/16 ,  H03K19/20 ,  H10B61/00 ,  H10N50/10 ,  H10N50/85

CPC classification number: H10N52/85 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H03K19/20 ,  H10B61/22 ,  H10N50/10 ,  H10N50/85

Abstract: In embodiments herein, probabilistic and deterministic logic devices include reduced symmetry materials, such as two-dimensional (2D) transition metal dichalcogenide (TMD) materials (e.g., NbSe2 or MoTe2).

公开(公告)号：US20240205908A1

公开(公告)日：2024-06-20

申请号：US18550093

申请日：2022-05-23

Applicant: Intel Corporation

Inventor： Yingyang Li ,  Yi Wang ,  Debdeep Chatterjee ,  Gang Xiong ,  Seunghee Han

IPC: H04W72/12 ,  H04W72/23

CPC classification number: H04W72/12 ,  H04W72/23

Abstract: Various embodiments may relate to physical downlink control channel (PDCCH) monitoring in association with cross-carrier scheduling. In particular, some embodiments are directed to scheduling a transmission on a primary cell (PCell) or primary secondary cell (PSCell) considering secondary cell (SCell) dormancy switching or SCell activation states. Other embodiments may be disclosed or claimed.

公开(公告)号：US20240205828A1

公开(公告)日：2024-06-20

申请号：US18083535

申请日：2022-12-18

Applicant: INTEL CORPORATION

Inventor： Venkateshan Udhayan ,  Nevo Idan ,  Leor Rom

IPC: H04W52/02 ,  H04W76/20

CPC classification number: H04W52/0235 ,  H04W76/20

Abstract: For example, an apparatus may include circuitry and logic configured to cause a wireless communication device to identify an end-to-end network latency of a data stream communicated between the wireless communication device and an endpoint via a wireless communication link between the wireless communication device and an Access Point (AP); and to set an idle timeout period for the wireless communication link based on the end-to-end network latency of the data stream. For example, the idle timeout period includes a time period after which the wireless communication device is to be allowed to switch the wireless communication link from an active mode to a power save mode when the wireless communication link is idle.

公开(公告)号：US20240205198A1

公开(公告)日：2024-06-20

申请号：US18288955

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Kapil Sood ,  Srinivasa Addepalli ,  Dong Guo ,  Sakari Poussa ,  Kailun Qin ,  Ismo Puustinen ,  Veronika Karperko

IPC: H04L9/40

CPC classification number: H04L63/0428 ,  H04L63/0823

Abstract: Various methods, systems, and use cases for securely managing, generating, and controlling access to keys in a service mesh are discussed herein. In various examples, key protection operations include service mesh signing key protection and service mesh communication key protection, for a secure transport session between services such as conducted with mutual transport layer security (mTLS). For instance, such key protection operations may be used to establish communications between the service host and another entity within the service mesh, in a secure transport session, based on use of a private key (secured using a confidential computing technology) in a secure enclave or other secure compute environment to sign one or more keys for the secure transport session.