公开(公告)号：US10305456B2

公开(公告)日：2019-05-28

申请号：US15605536

申请日：2017-05-25

Applicant: STMicroelectronics SA

Inventor： Hanae Zegmout ,  Denis Pache ,  Stephane Le Tual

IPC: H03K3/42 ,  H01S5/00 ,  H03M1/00

Abstract: The present disclosure relates to a device for converting an optical pulse to an electronic pulse includes a photoresistor having first and second terminals and being capable of receiving a pulsed laser signal arising from a mode-locked laser source The first terminal is linked to a node for applying a reference potential via a resistive element and a capacitive element connected in parallel. The second terminal is connected to a node for applying a supply potential.

公开(公告)号：US10263603B2

公开(公告)日：2019-04-16

申请号：US15462494

申请日：2017-03-17

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Pascal Urard ,  Alok Kumar Tripathi

IPC: H03K3/012 ,  H03K3/356 ,  H03K19/00 ,  H03K3/0233 ,  H03K3/3562

Abstract: The synchronous retention flip-flop circuit comprises a first circuit module suitable for being powered by an interruptible power source and a second circuit module suitable for being powered by a permanent power source. The first circuit module includes first and second latch stages, which are configured to store at least one datum while said interruptible power source is supplying power, transmitting means suitable for being controlled by a second control signal and configured to deliver said at least one datum to the second circuit module before an interruption of said interruptible power source, the second circuit module being configured to preserve said at least one datum during said interruption, and restoring means suitable for being controlled by a first control signal and configured to restore said at least one datum at the end of said interruption. Only the second control signal remains active during interruption of the interruptible power source.

公开(公告)号：US10249427B2

公开(公告)日：2019-04-02

申请号：US15223148

申请日：2016-07-29

Applicant: STMICROELECTRONICS SA

Inventor： Vincent Knopik

IPC: H01Q1/24 ,  H01F27/28 ,  H01L23/522 ,  H03H7/42 ,  H01F27/29 ,  H01F38/14 ,  H01F41/04 ,  H01F41/10 ,  H01Q1/36 ,  H01Q1/48 ,  H01Q1/50 ,  H01Q7/00

Abstract: A transformer of the symmetric-asymmetric type includes comprising a primary inductive circuit and a secondary inductive circuit formed in a same plane by respective interleaved and stacked metal tracks. A first crossing region includes a pair of connection plates facing one another, with each connection plate having a rectangular shape that is wider than the metal tracks, and diagonally connected to tracks of the secondary inductive circuit.

公开(公告)号：US10186022B2

公开(公告)日：2019-01-22

申请号：US15636294

申请日：2017-06-28

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics SA

Inventor： Mahesh Chandra ,  Antoine Drouot

IPC: G06T5/20 ,  G06T11/60 ,  G06T5/00 ,  G06K9/46 ,  G06K9/56

Abstract: Various embodiments provide an optimized image filter. The optimized image and video obtains an input image and selects a target pixel for modification. Difference values are then determined between the selected target pixel and each reference pixel of a search area. Subsequently, a weighting function is used to determine weight values for each of the reference pixels of the search area based on their respective difference value. The selected target pixel is then modified by the optimized image filter using the determined weight values. A new target pixel in an apply patch is then selected for modification. The new target pixel is modified using the previously determined weight values reassigned to a new set of reference pixels. The previously determined weight values are reassigned to the new set of reference pixels based on each of the new set of reference pixels' position relative to the new target pixel.

公开(公告)号：US10062681B2

公开(公告)日：2018-08-28

申请号：US15591565

申请日：2017-05-10

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  Centre National de la Recherche Scientifique

Inventor： Yohann Solaro ,  Sorin Cristoloveanu ,  Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/74 ,  H01L29/749 ,  H01L29/747 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L27/12

CPC classification number: H01L27/0262 ,  H01L27/1203 ,  H01L29/1012 ,  H01L29/42308 ,  H01L29/66477 ,  H01L29/7436 ,  H01L29/747 ,  H01L29/749 ,  H01L29/78 ,  H01L29/7833

Abstract: A protection device for protecting an IC against electrostatic discharge includes a buried insulant layer having a thickness that is no greater than fifty nanometers with bipolar transistors arranged thereon, one of which is NPN and the other of which is PNP. A base of one merges with a collector of the other. The transistors selectively conduct a discharge current between electrodes. A first semiconductor ground plane under the buried insulant layer is capable of being electrically biased and extends underneath the base of the first bipolar transistor. The ground plane and a base of one transistor have the same doping. However, its dopant density is at least tenfold greater than that of the base.

公开(公告)号：US20180166318A1

公开(公告)日：2018-06-14

申请号：US15892696

申请日：2018-02-09

Applicant: STMicroelectronics SA

Inventor： Didier Dutartre ,  Herve Jaouen

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/7624 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/763 ,  H01L29/04

Abstract: A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.

公开(公告)号：US09997512B2

公开(公告)日：2018-06-12

申请号：US15199454

申请日：2016-06-30

Applicant: STMicroelectronics S.A.

Inventor： Jean Jimenez ,  Boris Heitz ,  Johan Bourgeat ,  Agustin Monroy Aguirre

IPC: H01L29/00 ,  H01L27/02 ,  H01L27/12 ,  H01L27/102 ,  H01L29/74 ,  H01L29/87

CPC classification number: H01L27/0262 ,  H01L27/1027 ,  H01L27/1203 ,  H01L29/74 ,  H01L29/7408 ,  H01L29/7436 ,  H01L29/87 ,  H01L2924/1301

Abstract: An electronic device includes a thyristor having an anode, a cathode, a first bipolar transistor disposed on the anode side. A second bipolar transistor is disposed on the cathode side. These two bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is coupled between the collector region and the emitter region of the second bipolar transistor. The transistor has a gate region connected to the cathode via a resistive semiconductor region incorporating at least a part of the base region of the second bipolar transistor.

公开(公告)号：US09978602B2

公开(公告)日：2018-05-22

申请号：US14923176

申请日：2015-10-26

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS (Crolles 2) SAS ,  STMICROELECTRONICS SA

Inventor： Heimanu Niebojewski ,  Yves Morand ,  Maud Vinet

IPC: H01L21/84 ,  H01L21/28 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L21/28123 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02645 ,  H01L21/02667 ,  H01L21/76205 ,  H01L21/7624 ,  H01L21/76248 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78603

Abstract: The invention relates to a method for manufacturing a transistor comprising the preparation of a stack of layers of the semiconductor on insulator type comprising at least one substrate on which an insulating layer and an initial semiconductor layer are successively disposed. The method includes the formation of at least one oxide pad extending from a top face of the insulating layer, the formation of an additional layer made from semiconductor material covering the oxide pad and intended to form a channel for the transistor, the formation of a gate stack above the oxide pad, and the formation of a source and drain on either side of the gate stack.

公开(公告)号：US20180108762A1

公开(公告)日：2018-04-19

申请号：US15840890

申请日：2017-12-13

Applicant: STMicroelectronics SA

Inventor： Pascal Chevalier

IPC: H01L29/732 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L21/308 ,  H01L29/737

CPC classification number: H01L29/732 ,  H01L21/308 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7371

Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening having sidewalls lined with an insulating sheath. A portion of the insulating sheath adjacent the base region is removed and a base contact region is formed by epitaxial material grown from a portion of the base region exposed by removal of the portion of the insulating sheath.

公开(公告)号：US20180097014A1

公开(公告)日：2018-04-05

申请号：US15722340

申请日：2017-10-02

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Vincent Barral ,  Nicolas Planes ,  Antoine Cros ,  Sebastien Haendler ,  Thierry Poiroux ,  Olivier Weber ,  Patrick Scheer

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  B82Y99/00

Abstract: An electronic chip includes FDSOI-type field-effect transistors. The transistor each have a channel region that is doped at an average level in a range from 1016 to 5*1017 atoms/cm3 with a conductivity type opposite to that of a conductivity type for the dopant in the drain and source regions.