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    Collimated beam channel with four lens optical surfaces
    71.
    发明授权
    Collimated beam channel with four lens optical surfaces 有权
    具有四个透镜光学表面的准直光束通道

    公开(公告)号：US08917997B2

    公开(公告)日：2014-12-23

    申请号：US13645627

    申请日：2012-10-05

    Applicant: Applied Micro Circuits Corporation

    Inventor： Benoit Sevigny

    IPC: H04B10/00

    CPC classification number: H04B10/2504 ,  G02B13/08 ,  G02B19/0014 ,  G02B19/0085 ,  G02B27/30 ,  H04B10/25

    Abstract: An optical system and method disclosed include a first lens component and a second lens component within the receive path or the transmit path. The first lens component includes at least two aspheric surfaces that oppose one another and generate a collimated beam channel. The second lens component generates a converging beam and magnifies the converging beam with a magnification factor that is different from a magnification factor in the other path, either the receive path or the transmit path. The receive path and the transmit path include symmetrical lengths and asymmetrical magnification factors.

    Abstract translation: 所公开的光学系统和方法包括在接收路径或发射路径内的第一透镜部件和第二透镜部件。 第一透镜部件包括至少两个彼此相对的非球面，并产生准直的光束通道。 第二透镜部件产生会聚光束，并以不同于另一路径（即接收路径或发送路径）中的放大因子的放大倍率来放大会聚光束。 接收路径和发送路径包括对称长度和不对称放大系数。

    METHOD AND APPARATUS FOR SMOOTHING JITTER GENERATED BY BYTE STUFFING
    72.
    发明申请
    METHOD AND APPARATUS FOR SMOOTHING JITTER GENERATED BY BYTE STUFFING 有权
    用于通过字节处理生成的扫描器的方法和装置

    公开(公告)号：US20140314192A1

    公开(公告)日：2014-10-23

    申请号：US13865843

    申请日：2013-04-18

    Applicant: Applied Micro Circuits Corporation

    Inventor： Yehuda AZENKOT ,  Timothy P. WALKER

    IPC: H04L7/00 ,  H04L1/00

    CPC classification number: H04L1/004 ,  H03L1/00 ,  H03L7/081 ,  H03L7/107 ,  H03L2207/50 ,  H04J3/076

    Abstract: Systems and methods for smoothing jitter generated by byte stuffing. A frequency synthesizer comprises a smoothing logic coupled with a PLL. The smoothing logic is configured to modify a phase error signal generated by a phase frequency detector into a distributed phase error signal that spread over multiple clock cycles. The distributed phase error signal is used to drive a DCO. The smoothing logic may comprise a ramping logic operable to generate a series of ramping values to substitute a phase difference in the phase error signal. The phase difference may correspond to a stuffing byte.

    Abstract translation: 用于平滑由字节填充产生的抖动的系统和方法。 频率合成器包括与PLL耦合的平滑逻辑。 平滑逻辑被配置为将由相位频率检测器产生的相位误差信号修改成在多个时钟周期上分布的分布相位误差信号。 分布相位误差信号用于驱动DCO。 平滑逻辑可以包括斜坡逻​​辑，其可操作以产生一系列斜坡值来代替相位误差信号中的相位差。 相位差可对应于填充字节。

    METHOD FOR USING A PHOTODETECTOR HAVING A BANDWIDTH TUNED HONEYCOMB CELL PHOTODIODE STRUCTURE
    73.
    发明申请
    METHOD FOR USING A PHOTODETECTOR HAVING A BANDWIDTH TUNED HONEYCOMB CELL PHOTODIODE STRUCTURE 审中-公开
    使用具有束带调谐蜂窝状细胞光电子结构的光电转换器的方法

    公开(公告)号：US20140209801A1

    公开(公告)日：2014-07-31

    申请号：US14171455

    申请日：2014-02-03

    Applicant: VOLEX PLC ,  APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Subhash Roy ,  Igor Zhovnirovsky ,  Sergey Vinogradov

    IPC: G01J1/44

    CPC classification number: G01J1/44 ,  H01L22/14 ,  H01L27/1446 ,  H01L31/00 ,  H01L31/02019 ,  H01L31/022408 ,  H01L31/03529 ,  H01L31/105 ,  H01L31/108 ,  H01L31/1085 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/00

    Abstract: A photodetector with a bandwidth-tuned cell structure is provided. The photodetector is fabricated from a semiconductor substrate that is heavily doped with a first dopant. A plurality of adjoining cavities is formed in the semiconductor substrate having shared cell walls. A semiconductor well is formed in each cavity, moderately doped with a second dopant opposite in polarity to the first dopant. A layer of oxide is grown overlying the semiconductor wells and an annealing process is performed. Then, metal pillars are formed that extend into each semiconductor well having a central axis aligned with an optical path. A first electrode is connected to the metal pillar of each cell, and a second electrode connected to the semiconductor substrate. The capacitance between the first and second electrodes decreases in response to forming an increased number of semiconductor wells with a reduced diameter, and forming metal pillars with a reduced diameter.

    Abstract translation: 提供具有带宽调谐单元结构的光电检测器。 光电检测器由重掺杂第一掺杂剂的半导体衬底制成。 在具有共享单元壁的半导体衬底中形成多个邻接的空腔。 在每个空腔中形成半导体阱，中等掺杂有与第一掺杂剂极性相反的第二掺杂剂。 生长覆盖在半导体阱上的一层氧化物，并进行退火处理。 然后，形成延伸到具有与光路对准的中心轴的每个半导体阱中的金属柱。 第一电极连接到每个电池的金属柱，以及连接到半导体衬底的第二电极。 响应于形成具有减小的直径的增加数量的半导体阱并且形成直径减小的金属柱，第一和第二电极之间的电容减小。

    High speed serializer using quadrature clocks
    74.
    发明授权
    High speed serializer using quadrature clocks 有权

    公开(公告)号：US10110334B2

    公开(公告)日：2018-10-23

    申请号：US15137187

    申请日：2016-04-25

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Vijay Gupta ,  Tarun Gupta

    IPC: H04J3/06 ,  H04L7/00 ,  H03M9/00 ,  H04J3/04

    Abstract: Techniques efficiently serialize multiple data streams using quadrature clocks. Serializer employs first, second, third, and fourth clock signals. Serializer receives multiple data streams via registers, with each of four paths comprising a register, buffer, and switch, with registers of first and fourth paths associated with third clock signal, and registers of second and third paths associated with first clock signal, and with switches of first and fourth paths associated with first clock signal, and switches of second and third paths associated with third clock signal. Switches of first and second paths transfer respective data bits to fifth switch via another buffer, wherein fifth switch is associated with a delayed second clock signal of a time delay component (TDC). Switches of third and fourth paths transfer respective data bits to sixth switch via another buffer, wherein sixth switch is associated with a delayed fourth clock signal of TDC.

    HIGH SPEED SERIALIZER USING QUADRATURE CLOCKS
    76.
    发明申请
    HIGH SPEED SERIALIZER USING QUADRATURE CLOCKS 审中-公开

    公开(公告)号：US20170310412A1

    公开(公告)日：2017-10-26

    申请号：US15137187

    申请日：2016-04-25

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Vijay Gupta ,  Tarun Gupta

    IPC: H04J3/06 ,  H04L7/00

    CPC classification number: H04J3/0691 ,  H03M9/00 ,  H04J3/047 ,  H04J3/0682 ,  H04J3/0685 ,  H04L7/0037

    Abstract: Techniques efficiently serialize multiple data streams using quadrature clocks. Serializer employs first, second, third, and fourth clock signals. Serializer receives multiple data streams via registers, with each of four paths comprising a register, buffer, and switch, with registers of first and fourth paths associated with third clock signal, and registers of second and third paths associated with first clock signal, and with switches of first and fourth paths associated with first clock signal, and switches of second and third paths associated with third clock signal. Switches of first and second paths transfer respective data bits to fifth switch via another buffer, wherein fifth switch is associated with a delayed second clock signal of a time delay component (TDC). Switches of third and fourth paths transfer respective data bits to sixth switch via another buffer, wherein sixth switch is associated with a delayed fourth clock signal of TDC.

    PACKAGE PROGRAMMABLE DECOUPLING CAPACITOR ARRAY
    80.
    发明申请
    PACKAGE PROGRAMMABLE DECOUPLING CAPACITOR ARRAY 有权
    包装可编程电容器阵列

    公开(公告)号：US20170063355A1

    公开(公告)日：2017-03-02

    申请号：US14838778

    申请日：2015-08-28

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Rich Thaik ,  Alfred Yeung ,  April Lambert ,  Jeremy Plunkett

    IPC: H03K5/1252 ,  H01L23/522 ,  H01L23/525

    CPC classification number: H03K5/1252 ,  H01L23/50 ,  H01L23/5223 ,  H01L23/525

    Abstract: A semiconductor chip allows for a selected amount of on-die decoupling capacitance to be connected to a very-large-scale integrated circuit (VLSI) system after the circuit design is complete. The semiconductor chip comprises an integrated circuit disposed on a packaging substrate, and a power distribution network that is electrically connectable to the integrated circuit via a programmable connectivity array via the packaging substrate.

    Abstract translation: 在电路设计完成之后，半导体芯片允许选定数量的管芯上的去耦电容连接到大规模集成电路（VLSI）系统。 半导体芯片包括设置在封装基板上的集成电路，以及经由可编程连接阵列经由封装基板与集成电路电连接的配电网。

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