N-type carrier enhancement in semiconductors
    73.
    发明授权
    N-type carrier enhancement in semiconductors 失效
    半导体中的N型载流子增强

    公开(公告)号:US08642431B2

    公开(公告)日:2014-02-04

    申请号:US13437036

    申请日:2012-04-02

    IPC分类号: H01L21/336

    摘要: A field effect transistor (FET) has a channel hosted in Ge. The FET has silicon-germanium (SiGe) source and drain formed by selective epitaxy. The SiGe source and drain exert a tensile stress onto the Ge channel. During forming of the SiGe source and drain, an n-type dopant species and a compensating species are being incorporated into the SiGe source and drain. The n-type dopant species and the compensating species are so selected that the size of the SiGe atomic radius is inbetween the dopant atomic radius and the compensating species atomic radius.

    摘要翻译: 场效应晶体管(FET)具有在Ge中托管的通道。 FET通过选择性外延形成硅 - 锗(SiGe)源极和漏极。 SiGe源极和漏极在Ge沟道上施加拉伸应力。 在形成SiGe源极和漏极期间,n型掺杂物质和补偿物质被并入到SiGe源极和漏极中。 选择n型掺杂物种类和补偿种类,使得SiGe原子半径的尺寸在掺杂剂原子半径和补偿物质原子半径之间。

    STRAINED SILICON AND STRAINED SILICON GERMANIUM ON INSULATOR
    76.
    发明申请
    STRAINED SILICON AND STRAINED SILICON GERMANIUM ON INSULATOR 有权
    绝缘体上的应变硅和应变硅锗

    公开(公告)号:US20140011328A1

    公开(公告)日:2014-01-09

    申请号:US13544093

    申请日:2012-07-09

    IPC分类号: H01L21/84 H01L21/8238

    摘要: A method for fabricating field effect transistors patterns a strained silicon layer formed on a dielectric layer of a substrate into at least one NFET region including at least a first portion of the strained silicon layer. The strained silicon layer is further patterned into at least one PFET region including at least a second portion of the strained silicon layer. A masking layer is formed over the first portion of the strained silicon layer. After the masking layer has been formed, the second strained silicon layer is transformed into a relaxed silicon layer. The relaxed silicon layer is transformed into a strained silicon germanium layer.

    摘要翻译: 用于制造场效应晶体管的方法将形成在衬底的电介质层上的应变硅层图案化成至少一个包括应变硅层的第一部分的NFET区域。 将应变硅层进一步图案化成至少一个包括应变硅层的至少第二部分的PFET区域。 在应变硅层的第一部分上形成掩模层。 在形成掩模层之后,将第二应变硅层转变成松弛的硅层。 松弛的硅层被转变成应变硅锗层。