公开(公告)号：US09406562B2

公开(公告)日：2016-08-02

申请号：US13005883

申请日：2011-01-13

Applicant: Jeffrey P. Bonn ,  Brent A. Goplen ,  Brian L. Kinsman ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Daniel S. Vanslette

Inventor： Jeffrey P. Bonn ,  Brent A. Goplen ,  Brian L. Kinsman ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Daniel S. Vanslette

IPC: H01L23/48 ,  H01L21/768 ,  G06F17/50

CPC classification number: H01L21/76898 ,  G06F17/5068 ,  G06F2217/80 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention provide an integrated circuit (IC) having reduced through silicon via (TSV)-induced stresses and related IC design structures and methods. In one embodiment, the invention includes a method of designing an integrated circuit (IC) having reduced substrate stress, the method including: placing in an IC design file a plurality of through silicon via (TSV) placeholder cells, each placeholder cell having an undefined TSV orientation; replacing a first portion of the plurality of TSV placeholder cells with a first group of TSV cells having a first orientation; and replacing a second portion of the plurality of TSV placeholder cells with a second group of TSV cells having a second orientation substantially perpendicular to the first orientation, wherein TSV cells having the first orientation and TSV cells having the second orientation are interspersed to reduce a TSV-induced stress in an IC substrate.

Abstract translation: 本发明的实施例提供了具有减少的通过硅通孔（TSV）的应力和相关IC设计结构和方法的集成电路（IC）。 在一个实施例中，本发明包括设计具有降低的衬底应力的集成电路（IC）的方法，所述方法包括：在IC设计文件中放置多个通过硅通孔（TSV）占位符单元，每个占位符单元具有未定义的 TSV方向 用具有第一取向的第一组TSV单元替换所述多个TSV占位符单元的第一部分; 以及用具有基本上垂直于第一取向的第二取向的第二组TSV单元替换多个TSV占位符单元的第二部分，其中具有第一取向的TSV单元和具有第二取向的TSV单元分散以减少TSV 在IC衬底中引起的应力。

公开(公告)号：US09111933B2

公开(公告)日：2015-08-18

申请号：US13474239

申请日：2012-05-17

Applicant: Gary D. Carpenter ,  Alan J. Drake ,  Rachel Gordin ,  Michael J. Shapiro ,  Edmund J. Sprogis

Inventor： Gary D. Carpenter ,  Alan J. Drake ,  Rachel Gordin ,  Michael J. Shapiro ,  Edmund J. Sprogis

IPC: H01F5/00 ,  H01F27/28 ,  H01L23/522 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L23/5227 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/30107 ,  Y10T29/49071 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A distributed active transformer is provided comprising a primary and a secondary winding. The primary winding comprises a first set of conductive vias extending in a direction between a first surface and a second surface of an element, a first set of first electrically conductive lines extending along the first surface, and a first set of second electrically conductive lines extending along the second surface. The secondary winding comprises a second set of conductive vias extending in a direction between the first surface and the second surface, a second set of first electrically conductive lines extending along the first surface, and a second set of second electrically conductive lines extending along the second surface. When energized, the primary winding generates magnetic flux extending in a direction parallel to the first surface and the second surface. The secondary winding receives energy transferred by the magnetic flux generated by the primary winding.

Abstract translation: 提供一种分布式有源变压器，其包括初级和次级绕组。 初级绕组包括在元件的第一表面和第二表面之间的方向上延伸的第一组导电通孔，沿着第一表面延伸的第一组第一导电线，以及延伸的第一组第二导电线 沿着第二个表面。 次级绕组包括在第一表面和第二表面之间的方向上延伸的第二组导电通孔，沿着第一表面延伸的第二组第一导电线，以及沿着第二表面延伸的第二组第二导电线 表面。 当通电时，初级绕组产生沿平行于第一表面和第二表面的方向延伸的磁通量。 次级绕组接收由初级绕组产生的磁通传递的能量。

公开(公告)号：US20130320521A1

公开(公告)日：2013-12-05

申请号：US13483663

申请日：2012-05-30

Applicant: Timothy H. DAUBENSPECK ,  Steven E. MOLIS ,  Gordon C. OSBORNE, JR. ,  Wolfgang SAUTER ,  Edmund J. SPROGIS

Inventor： Timothy H. DAUBENSPECK ,  Steven E. MOLIS ,  Gordon C. OSBORNE, JR. ,  Wolfgang SAUTER ,  Edmund J. SPROGIS

IPC: H01L21/768 ,  H01L23/498

CPC classification number: H01L21/6835 ,  H01L21/486 ,  H01L21/76829 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2225/06513 ,  H01L2225/06517 ,  Y10S438/976 ,  H01L2924/014

Abstract: A releasable buried layer for 3-D fabrication and methods of manufacturing is disclosed. The method includes forming an interposer structure which includes forming a carbon rich dielectric releasable layer over a wafer. The method further includes forming back end of the line (BEOL) layers over the carbon rich dielectric layer, including wiring layers and solder bumps. The method further includes bonding the solder bumps to a substrate using flip chip processes. The flip chip processes comprises reflowing the solder bumps and rapidly cooling down the solder bumps which releases the carbon rich dielectric releasable layer from the wafer.

Abstract translation: 公开了用于3-D制造的可释放掩埋层和制造方法。 该方法包括形成中间层结构，其包括在晶片上形成富含碳的电介质可剥离层。 该方法还包括在富含碳的电介质层上形成线（BEOL）层的后端，包括布线层和焊料凸块。 该方法还包括使用倒装芯片工艺将焊料凸块接合到衬底上。 倒装芯片工艺包括回流焊料凸块并快速冷却焊料凸块，从而将富碳介电层可释放层从晶片上释放出来。

公开(公告)号：US20120214280A1

公开(公告)日：2012-08-23

申请号：US13460871

申请日：2012-05-01

Applicant: Douglas D. COOLBAUGH ,  Ebenezer E. ESHUN ,  Terence B. HOOK ,  Robert M. RASSEL ,  Edmund J. SPROGIS ,  Anthony K. STAMPER ,  William J. MURPHY

Inventor： Douglas D. COOLBAUGH ,  Ebenezer E. ESHUN ,  Terence B. HOOK ,  Robert M. RASSEL ,  Edmund J. SPROGIS ,  Anthony K. STAMPER ,  William J. MURPHY

IPC: H01L21/50

CPC classification number: H01C7/1013 ,  H01C1/084 ,  H01L2924/0002 ,  Y10T29/49083 ,  Y10T29/49085 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2924/00

Abstract: A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.

Abstract translation: 提供带散热片的电阻。 散热器包括具有导热性高的金属或其它热导体的导电路径。 为了避免使用热导体将电阻器短路接地，在热导体和电阻体之间插入有一层薄导电电绝缘体。 因此，电阻器可承载大量的电流，因为高导电性热导体将热量从电阻器传导到散热器。 除了降低寄生电容和其他寄生电效应之外，提供各种配置的导热体和散热片，提供良好的导热性能，这将降低电阻器的高频响应。

公开(公告)号：US08198734B2

公开(公告)日：2012-06-12

申请号：US12550494

申请日：2009-08-31

Applicant: Brent A. Anderson ,  Paul S. Andry ,  Edmund J. Sprogis ,  Cornelia K. Tsang

Inventor： Brent A. Anderson ,  Paul S. Andry ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC: H01L27/12 ,  H01L29/40 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68368 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01019 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/19041 ,  H01L2924/19043

Abstract: A silicon-on-insulator (SOI) structure is provided for forming through vias in a silicon wafer carrier structure without backside lithography. The SOI structure includes the silicon wafer carrier structure bonded to a silicon substrate structure with a layer of buried oxide and a layer of nitride separating these silicon structures. Vias are formed in the silicon carrier structure and through the oxide layer to the nitride layer and the walls of the via are passivated. The vias are filled with a filler material of either polysilicon or a conductive material. The substrate structure is then etched back to the nitride layer and the nitride layer is etched back to the filler material. Where the filler material is polysilicon, the polysilicon is etched away forming an open via to the top surface of the carrier wafer structure. The via is then backfilled with conductive material.

Abstract translation: 提供绝缘体上硅（SOI）结构，用于在硅晶片载体结构中形成通孔，而无需背面光刻。 SOI结构包括用一层掩埋氧化物结合到硅衬底结构的硅晶片载体结构和分离这些硅结构的氮化物层。 在硅载体结构中形成通孔，并且通过氧化物层到达氮化物层，并且通孔的壁被钝化。 通孔填充有多晶硅或导电材料的填充材料。 然后将衬底结构回蚀刻到氮化物层，氮化物层被回蚀刻到填充材料上。 当填充材料是多晶硅时，多晶硅被蚀刻掉，形成开口通孔到载体晶片结构的顶表面。 然后通孔用导电材料回填。

公开(公告)号：US20120137515A1

公开(公告)日：2012-06-07

申请号：US13369414

申请日：2012-02-09

Applicant: Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

Inventor： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

IPC: H01K3/10

CPC classification number: H01L21/76898 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts.

Abstract translation: 提出了通过晶片通孔（TWV）和标准触点在两个单独的工艺中形成以防止铜第一金属层挤压和短路的方法。 在一个实施例中，一种方法可以包括将TWV形成到衬底上并且在衬底上形成第一介电层; 在所述衬底和所述TWV上形成第二电介质层; 通过所述第二电介质层形成至少一个接触到所述TWV和与所述衬底上的其它结构的至少一个接触; 以及在所述第二电介质层上形成第一金属布线层，所述第一金属布线层与所述触点中的至少一个接触。

公开(公告)号：US08166651B2

公开(公告)日：2012-05-01

申请号：US12181359

申请日：2008-07-29

Applicant: Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

Inventor： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

IPC: H01K3/10 ,  H05K3/02 ,  H05K3/10 ,  H01L29/40

CPC classification number: H01L21/76898 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a through wafer via including forming the through wafer via (TWV) into a substrate and through a first dielectric layer over the substrate; planarizing the first dielectric layer using a chemical mechanical polish before forming a second dielectric layer; forming the second dielectric layer over the substrate and the TWV; forming at least one first contact through the second dielectric layer and to the TWV; forming at least one second contact through the second dielectric layer and the first dielectric layer directly and electrically connected to another structure upon the substrate; and forming a first metal wiring layer directly over the second dielectric layer, the first metal wiring layer directly and physically contacting the at least one first contact and the at least one second contact.

Abstract translation: 一种形成贯穿晶片通孔的方法，包括通过（TWV）形成贯穿晶片进入衬底并穿过衬底上的第一介电层; 在形成第二电介质层之前，使用化学机械抛光平面化第一介电层; 在所述衬底和所述TWV上形成所述第二电介质层; 通过所述第二介电层和所述TWV形成至少一个第一接触; 通过所述第二电介质层和所述第一介电层形成至少一个第二接触，并且在所述衬底上直接电连接到另一结构; 以及直接在所述第二电介质层上方形成第一金属布线层，所述第一金属布线层直接地和物理地接触所述至少一个第一触点和所述至少一个第二触点。

公开(公告)号：US20120091585A1

公开(公告)日：2012-04-19

申请号：US13312456

申请日：2011-12-06

Applicant: Leena P. Buchwalter ,  Paul S. Andry ,  Matthew J. Farinelli ,  Sherif A. Goma ,  Raymond R. Horton ,  Edmund J. Sprogis

Inventor： Leena P. Buchwalter ,  Paul S. Andry ,  Matthew J. Farinelli ,  Sherif A. Goma ,  Raymond R. Horton ,  Edmund J. Sprogis

IPC: H01L23/498 ,  H01L23/485

CPC classification number: H01L21/67092 ,  H01L21/67132 ,  H01L21/6835 ,  H01L21/6836 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2224/11003 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  Y10S414/139 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.

Abstract translation: 提供了用于避免载波边缘破裂的集成电路模块的激光释放和玻璃切屑去除工艺。

公开(公告)号：US08136084B2

公开(公告)日：2012-03-13

申请号：US12555981

申请日：2009-09-09

Applicant: Donald R. Dean, Jr. ,  Peter J. Lindgren ,  Glen L. Miles ,  Edmund J. Sprogis ,  Anthony K. Stamper

Inventor： Donald R. Dean, Jr. ,  Peter J. Lindgren ,  Glen L. Miles ,  Edmund J. Sprogis ,  Anthony K. Stamper

IPC: G06F17/52

CPC classification number: H01L21/76898 ,  G06F17/5072

Abstract: A portion of an IC layout that includes a plurality of through silicon vias (TSVs) is evaluated to identify linearly aligned TSVs. The portion of the IC layout is modified to reduce a number of the linearly aligned TSVs, resulting in less wafer breakage.

Abstract translation: 评估包括多个贯穿硅通孔（TSV）的IC布局的一部分以识别线性对准的TSV。 修改IC布局的部分以减少多个线性对齐的TSV，导致较少的晶片断裂。

公开(公告)号：US20110180896A1

公开(公告)日：2011-07-28

申请号：US12692983

申请日：2010-01-25

Applicant: Gerd Pfeiffer ,  Haizhou Yin ,  Edmund J. Sprogis ,  Subramanian Iyer ,  Zhibin Ren ,  Dae-Gyu Park ,  Oleg Gluschenkov

Inventor： Gerd Pfeiffer ,  Haizhou Yin ,  Edmund J. Sprogis ,  Subramanian Iyer ,  Zhibin Ren ,  Dae-Gyu Park ,  Oleg Gluschenkov

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76256

Abstract: A method of forming a bonded wafer structure includes providing a first semiconductor wafer substrate having a first silicon oxide layer at the top surface of the first semiconductor wafer substrate; providing a second semiconductor wafer substrate; forming a second silicon oxide layer on the second semiconductor wafer substrate; forming a silicon nitride layer on the second silicon oxide layer; and bringing the first silicon oxide layer of the first semiconductor wafer substrate into physical contact with the silicon nitride layer of the second semiconductor wafer substrate to form a bonded interface between the first silicon oxide layer and the silicon nitride layer. Alternatively, a third silicon oxide layer may be formed on the silicon nitride layer before bonding. A bonded interface is then formed between the first and third silicon oxide layers. A bonded wafer structure formed by such a method is also provided.

Abstract translation: 形成接合晶片结构的方法包括：在第一半导体晶片衬底的顶表面上提供具有第一氧化硅层的第一半导体晶片衬底; 提供第二半导体晶片衬底; 在所述第二半导体晶片衬底上形成第二氧化硅层; 在所述第二氧化硅层上形成氮化硅层; 并且使第一半导体晶片衬底的第一氧化硅层与第二半导体晶片衬底的氮化硅层物理接触以在第一氧化硅层和氮化硅层之间形成键合界面。 或者，可以在接合之前在氮化硅层上形成第三氧化硅层。 然后在第一和第三氧化硅层之间形成键合界面。 还提供了通过这种方法形成的接合晶片结构。