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    Semiconductor memory device including recessed control gate electrode
    71.
    发明申请
    Semiconductor memory device including recessed control gate electrode 失效
    半导体存储器件包括凹入控制栅电极

    公开(公告)号：US20080093662A1

    公开(公告)日：2008-04-24

    申请号：US11808982

    申请日：2007-06-14

    申请人： Sang-jin Park ,  Kwang-soo Seol ,  Yoon-dong Park ,  Sang-min Shin ,  In-jun Hwang ,  Sang-moo Choi ,  Ju-hee Park

    发明人： Sang-jin Park ,  Kwang-soo Seol ,  Yoon-dong Park ,  Sang-min Shin ,  In-jun Hwang ,  Sang-moo Choi ,  Ju-hee Park

    IPC分类号： H01L29/792

    CPC分类号： H01L29/42324 ,  G11C16/0408 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42336 ,  H01L29/4234 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

    摘要： A semiconductor memory device may include a semiconductor substrate, at least one control gate electrode, at least one storage node layer, at least one tunneling insulating layer, at least one blocking insulating layer, and/or first and second channel regions. The at least one control gate electrode may be recessed into the semiconductor substrate. The at least one storage node layer may be between a sidewall of the at least one control gate electrode and the semiconductor substrate. The at least one tunneling insulating layer may be between the at least one storage node layer and the at least one control gate electrode. The at least one blocking insulating layer may be between the storage node layer and the control gate electrode. The first and second channel regions may be between the at least one tunneling insulating layer and the semiconductor substrate to surround at least a portion of the sidewall of the control gate electrode and/or may be separated from each other.

    摘要翻译： 半导体存储器件可以包括半导体衬底，至少一个控制栅电极，至少一个存储节点层，至少一个隧道绝缘层，至少一个阻挡绝缘层和/或第一和第二沟道区。 至少一个控制栅电极可以凹进到半导体衬底中。 所述至少一个存储节点层可以在所述至少一个控制栅电极的侧壁和所述半导体衬底之间。 所述至少一个隧道绝缘层可以在所述至少一个存储节点层和所述至少一个控制栅电极之间。 所述至少一个阻挡绝缘层可以在所述存储节点层和所述控制栅电极之间。 第一和第二沟道区可以在至少一个隧道绝缘层和半导体衬底之间，以围绕控制栅电极的侧壁的至少一部分和/或可以彼此分离。

    VALVE AND MICRO FLUID PUMP HAVING THE SAME
    72.
    发明申请
    VALVE AND MICRO FLUID PUMP HAVING THE SAME 有权
    阀门和微型流体泵具有相同的功能

    公开(公告)号：US20080075605A1

    公开(公告)日：2008-03-27

    申请号：US11617865

    申请日：2006-12-29

    申请人： Duck-jong Kim ,  Yun-wook Hwang ,  Yu-chang Kim ,  Sang-jin Park ,  Pil-woo Heo ,  Eui-soo Yoon ,  Deuk-yong Koh

    发明人： Duck-jong Kim ,  Yun-wook Hwang ,  Yu-chang Kim ,  Sang-jin Park ,  Pil-woo Heo ,  Eui-soo Yoon ,  Deuk-yong Koh

    IPC分类号： F04F1/06

    CPC分类号： F04F1/06 ,  F04B19/006 ,  F04B53/141 ,  Y10T137/4643

    摘要： Disclosed herein are a valve and a micro fluid pump having the same. The valve is mounted in a micro fluid pump having a capillary tube, to which a gas supply unit and a fluid transfer pipe are connected, for controlling the introduction and the discharge of fluid. The valve includes a discharge pipe filled with liquid such that the discharge pipe has a predetermined resistance pressure and constructed in a structure in which one end of the discharge pipe is connected to the capillary tube such that the discharge pipe communicates with the interior of the capillary tube, and the other end of the discharge pipe is open, thereby allowing gas out of the capillary tube through the discharge pipe when a gas pressure in the capillary tube exceeds the resistance pressure of the discharge pipe.

    摘要翻译： 本文公开了具有该阀和微流体泵的阀。 阀安装在具有毛细管的微流体泵中，气体供给单元和流体输送管连接到毛细管上，用于控制流体的引入和排出。 阀包括填充有液体的排出管，使得排出管具有预定的电阻压力，并且构造成排出管的一端连接到毛细管的结构，使得排出管与毛细管的内部连通 管，排出管的另一端开放，从而当毛细管中的气体压力超过排出管的阻力压力时，通过排出管使气体从毛细管流出。

    Stacked semiconductor devices and methods of manufacturing the same
    73.
    发明申请
    Stacked semiconductor devices and methods of manufacturing the same 失效
    叠层半导体器件及其制造方法

    公开(公告)号：US20080023770A1

    公开(公告)日：2008-01-31

    申请号：US11823765

    申请日：2007-06-28

    申请人： Kyoung-Seok Kim ,  Kong-Soo Lee ,  Sang-Jin Park ,  Sung-Kwan Kang ,  Ko-Eun Lee

    发明人： Kyoung-Seok Kim ,  Kong-Soo Lee ,  Sang-Jin Park ,  Sung-Kwan Kang ,  Ko-Eun Lee

    IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L23/58

    CPC分类号： H01L27/0688 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28556 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/8221 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108

    摘要： The stacked semiconductor device includes a semiconductor substrate, a multi-layered insulation layer pattern having at least two insulation layer patterns and an opening, an active layer pattern formed on each of the insulation layer patterns, a first plug including single crystalline silicon-germanium, a second plug including single crystalline silicon, and a wiring electrically connected to the first plug and sufficiently filling up the opening. The insulation layer patterns are vertically stacked on the semiconductor substrate and the opening exposes an upper face of the semiconductor substrate. A side portion of the active layer pattern is exposed by the opening. The first plug is formed on the upper face of the semiconductor substrate to partially fill the opening. The second plug is partially formed on the first plug, and has substantially the same interface as that of the first plug.

    摘要翻译： 叠层半导体器件包括半导体衬底，具有至少两个绝缘层图案和开口的多层绝缘层图案，形成在每个绝缘层图案上的有源层图案，包括单晶硅锗的第一插头， 包括单晶硅的第二插头和电连接到第一插头并充分填满开口的布线。 绝缘层图案垂直堆叠在半导体衬底上，并且开口暴露半导体衬底的上表面。 有源层图案的侧面部分由开口露出。 第一插头形成在半导体衬底的上表面上以部分地填充开口。 第二插头部分地形成在第一插头上，并且具有与第一插头基本相同的界面。

    Nonvolatile memory devices including floating gates formed of silicon nano-crystals and methods of manufacturing the same
    75.
    发明申请
    Nonvolatile memory devices including floating gates formed of silicon nano-crystals and methods of manufacturing the same 审中-公开
    包括由硅纳米晶体形成的浮动栅极的非易失性存储器件及其制造方法

    公开(公告)号：US20070267679A1

    公开(公告)日：2007-11-22

    申请号：US11723020

    申请日：2007-03-15

    申请人： Young-kwan Cha ,  Suk-ho Choi ,  Kyu-il Han ,  Young-soo Park ,  Sang-jin Park ,  Yong-min Park

    发明人： Young-kwan Cha ,  Suk-ho Choi ,  Kyu-il Han ,  Young-soo Park ,  Sang-jin Park ,  Yong-min Park

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L29/42332 ,  B82Y10/00 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7881

    摘要： A memory device includes a gate stack on a substrate. The gate stack is disposed between a source and a drain. The gate stack includes a tunneling film, storage node, and control oxide film. A thickness of the control oxide film is greater than or equal to about 5 nm and less than or equal to about 30 nm. A method of manufacturing a memory device, including a gate stack on a substrate, wherein the gate stack is disposed between a source and a drain, includes: sequentially forming a tunneling film, a first silicon-rich oxide film, and a control oxide film on the substrate, wherein the first silicon-rich oxide film comprises a SiOx film (1.5

    摘要翻译： 存储器件包括在衬底上的栅叠层。 栅极堆叠设置在源极和漏极之间。 栅极堆叠包括隧道膜，存储节点和控制氧化物膜。 控制氧化物膜的厚度大于或等于约5nm且小于或等于约30nm。 一种制造存储器件的方法，其包括在衬底上的栅极堆叠，其中所述栅极堆叠设置在源极和漏极之间，包括：顺序地形成隧道膜，第一富硅氧化物膜和控制氧化物膜 在所述衬底上，其中所述第一富氧氧化物膜包括SiO x薄膜（1.5

    Memory device and method for operating the same
    76.
    发明申请
    Memory device and method for operating the same 失效
    存储器件及其操作方法

    公开(公告)号：US20070211533A1

    公开(公告)日：2007-09-13

    申请号：US11704204

    申请日：2007-02-09

    申请人： Sang-Jin Park ,  Young-Soo Park ,  Sang-Min Shin ,  Young-Kwan Cha

    发明人： Sang-Jin Park ,  Young-Soo Park ,  Sang-Min Shin ,  Young-Kwan Cha

    IPC分类号： G11C16/04 ,  G11C11/34

    CPC分类号： G11C16/0416 ,  B82Y10/00 ,  G11C2216/06 ,  H01L29/42332 ,  H01L29/7881

    摘要： A memory device and method for operating the same are provided. The example method may be directed to a method of performing a memory operation on a memory device, and may include applying a negative voltage bias to the memory device during a programming operation of the memory device and applying a positive voltage bias to the memory device during an erasing operation of the memory device. The example memory device may include a substrate and a gate structure formed on the substrate, the gate structure exhibiting a faster flat band voltage shift under a negative voltage bias than under a positive voltage bias, the gate structure receiving a negative voltage bias during a programming of the memory device and receiving a positive voltage bias during an erasing operation of the memory device.

    摘要翻译： 提供了一种用于操作该存储器件的存储器件和方法。 示例性方法可以针对在存储器件上执行存储器操作的方法，并且可以包括在存储器件的编程操作期间向存储器件施加负电压偏压，并且在存储器件期间向存储器件施加正电压偏压 存储器件的擦除操作。 示例性存储器件可以包括衬底和形成在衬底上的栅极结构，栅极结构在负电压偏压下比在正电压偏压下表现出更快的平带电压偏移，栅极结构在编程期间接收负电压偏置 并且在存储器件的擦除操作期间接收正电压偏置。

    Semiconductor memory device having an alloy metal gate electrode and method of manufacturing the same
    77.
    发明申请
    Semiconductor memory device having an alloy metal gate electrode and method of manufacturing the same 审中-公开
    具有合金金属栅电极的半导体存储器件及其制造方法

    公开(公告)号：US20070190721A1

    公开(公告)日：2007-08-16

    申请号：US11655180

    申请日：2007-01-19

    申请人： Young-kwan Cha ,  Young-soo Park ,  Kwang-soo Seol ,  Sang-jin Park ,  Sang-min Shin

    发明人： Young-kwan Cha ,  Young-soo Park ,  Kwang-soo Seol ,  Sang-jin Park ,  Sang-min Shin

    IPC分类号： H01L21/336

    CPC分类号： H01L29/513 ,  H01L21/28088 ,  H01L29/40117 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792

    摘要： A semiconductor memory device having an alloy gate electrode layer and method of manufacturing the same are provided. The semiconductor memory device may include a semiconductor substrate having a first impurity region and a second impurity region. The semiconductor memory device may include a gate structure formed on the semiconductor substrate and contacting the first and second impurity regions. The gate structure may include an alloy gate electrode layer formed of a first metal and a second metal. The first metal may be a noble metal. The second metal may include at least one of aluminum (Al) and titanium (Ti), gallium (Ga), indium (In), tin (Sb), thallium (Tl), bismuth (Bi) and lead (Pb).

    摘要翻译： 提供了具有合金栅电极层的半导体存储器件及其制造方法。 半导体存储器件可以包括具有第一杂质区和第二杂质区的半导体衬底。 半导体存储器件可以包括形成在半导体衬底上并与第一和第二杂质区接触的栅极结构。 栅极结构可以包括由第一金属和第二金属形成的合金栅极电极层。 第一种金属可能是贵金属。 第二金属可以包括铝（Al）和钛（Ti），镓（Ga），铟（In），锡（Sb），铊（Tl），铋（Bi）和铅（Pb）中的至少一种。

    LIGHT SENSING PANEL, AND LIQUID CRYSTAL DISPLAY APPARATUS HAVING THE SAME
    78.
    发明申请
    LIGHT SENSING PANEL, AND LIQUID CRYSTAL DISPLAY APPARATUS HAVING THE SAME 有权
    感光板和液晶显示装置

    公开(公告)号：US20070187720A1

    公开(公告)日：2007-08-16

    申请号：US11691048

    申请日：2007-03-26

    申请人： Sang-Jin Park ,  Kee-Han Uh ,  Young-Bae Jung ,  Jong-Whan Cho ,  Young-Jun Choi

    发明人： Sang-Jin Park ,  Kee-Han Uh ,  Young-Bae Jung ,  Jong-Whan Cho ,  Young-Jun Choi

    IPC分类号： H01L27/10 ,  H01L29/73

    CPC分类号： H01L27/1214 ,  G02F1/1362 ,  G02F2001/13312

    摘要： A light sensing panel includes a scan line transmitting a scan signal, a power source line transmitting a bias voltage, a readout line transmitting a light sensing signal and a light sensing device. The light sensing device includes a control electrode that is electrically connected to the scan line to receive the scan signal, a first current electrode that is electrically connected to the power source line to receive the bias voltage, and a second current electrode that is electrically connected to the readout line to apply a light sensing signal to the readout line when the light sensing signal senses an external light. The light sensing panel requires only one thin film transistor in order to detect a position wherein the external light is incident. Therefore, electrical coupling between devices is reduced and aperture ratio is increased, thereby enhancing a display quality.

    摘要翻译： 光检测面板包括发送扫描信号的扫描线，发送偏置电压的电源线，发送感光信号的读出线和感光装置。 光感测装置包括电连接到扫描线以接收扫描信号的控制电极，电连接到电源线以接收偏置电压的第一电流电极和电连接的第二电流电极 到读出线，以便当感光信号感测外部光时，将光感测信号施加到读出线。 为了检测外部光入射的位置，光检测面板仅需要一个薄膜晶体管。 因此，器件之间的电耦合减小并且孔径比增加，从而提高显示质量。