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公开(公告)号：US20190378514A1
公开(公告)日：2019-12-12
申请号：US16546574
申请日：2019-08-21
Applicant: Apple Inc.
Inventor： Timothy J. Millet , Manu Gulati , Michael F. Culbert
IPC: G10L15/28 , G06F1/3228 , G06F1/3287 , G06F1/32 , G10L15/22 , G06F3/16
Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.
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公开(公告)号：US20190286519A1
公开(公告)日：2019-09-19
申请号：US16405362
申请日：2019-05-07
Applicant: Apple Inc.
Inventor： Manu Gulati , Sukalpa Biswas , Jeffrey R. Wilcox , Farid Nemati
Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.
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公开(公告)号：US10298511B2
公开(公告)日：2019-05-21
申请号：US15246046
申请日：2016-08-24
Applicant: Apple Inc.
Inventor： Manu Gulati , Christopher D. Shuler , Benjamin K. Dodge , Thejasvi M. Vijayaraj , Harshavardhan Kaushikkar , Yang Yang , Rong Z. Hu , Srinivasa R. Sridharan , Wolfgang H. Klingauf , Neeraj Parik
IPC: H04W72/12 , H04L12/863 , G06F13/16 , G06F9/54 , H04L12/865
Abstract: In some embodiments, a system includes a memory system, plurality of computing devices, and plurality of queues. The plurality of computing devices perform actions dependent on data stored at the memory device, where traffic between the plurality of computing devices and the memory device has at least a first priority level and a second priority level. The first priority level is higher than the second priority level. The plurality of queues pass data between the memory device and the plurality of computing devices. A particular queue allocates a first portion of the particular queue to traffic having the first priority level and allocates a second portion of the particular queue to traffic having the first priority level and to traffic having the second priority level.
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公开(公告)号：US20180350369A1
公开(公告)日：2018-12-06
申请号：US16101603
申请日：2018-08-13
Applicant: Apple Inc.
Inventor： Timothy J. Millet , Manu Gulati , Michael F. Culbert
CPC classification number: G10L15/28 , G06F1/32 , G06F1/3228 , G06F1/3287 , G06F3/165 , G10L15/22 , G10L25/48 , G10L2015/088 , Y02D10/171
Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.
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公开(公告)号：US20180313673A1
公开(公告)日：2018-11-01
申请号：US16019087
申请日：2018-06-26
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. de Cesare , Anand Dalal
CPC classification number: G01D9/00 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F13/1689 , Y02D10/122 , Y02D10/171 , Y02D50/20
Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
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Patent Agency Ranking
公开(公告)号：US10102607B2
公开(公告)日：2018-10-16
申请号：US15692469
申请日：2017-08-31
Applicant: Apple Inc.
Inventor： Timothy J. Millet , Manu Gulati , Arthur L. Spence , Gurjeet S. Saund , Robert P. Esser
Abstract: One embodiment may include media circuits, an application processor, a direct memory access circuit (DMA), and a media managing circuit. The application processor may issue media commands into a queue. The media managing circuit may retrieve a first media command, set the DMA to copy data associated with the first media command to the first media circuit, and send the first media command to the first media circuit. While the first media command is being executed, the media managing circuit may also retrieve a second media command, determine that the second media command utilizes data that is dependent on a completion of the first media command, and set the DMA to copy data from the first media circuit to the second media circuit. After the first media command has been completed, the media managing circuit may also send the second media command to the second media circuit.
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公开(公告)号：US20180063016A1
公开(公告)日：2018-03-01
申请号：US15246046
申请日：2016-08-24
Applicant: Apple Inc.
Inventor： Manu Gulati , Christopher D. Shuler , Benjamin K. Dodge , Thejasvi M. Vijayaraj , Harshavardhan Kaushikkar , Yang Yang , Rong Z. Hu , Srinivasa R. Sridharan , Wolfgang H. Klingauf , Neeraj Parik
IPC: H04L12/863
CPC classification number: H04L47/6295 , G06F9/546 , G06F13/1642 , H04L47/6275
Abstract: In some embodiments, a system includes a memory system, plurality of computing devices, and plurality of queues. The plurality of computing devices perform actions dependent on data stored at the memory device, where traffic between the plurality of computing devices and the memory device has at least a first priority level and a second priority level. The first priority level is higher than the second priority level. The plurality of queues pass data between the memory device and the plurality of computing devices. A particular queue allocates a first portion of the particular queue to traffic having the first priority level and allocates a second portion of the particular queue to traffic having the first priority level and to traffic having the second priority level.
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公开(公告)号：US20170365034A1
公开(公告)日：2017-12-21
申请号：US15692469
申请日：2017-08-31
Applicant: Apple Inc.
Inventor： Timothy J. Millet , Manu Gulati , Arthur L. Spence , Gurjeet S. Saund , Robert P. Esser
CPC classification number: G06T1/20 , G06F9/4893 , G06F9/52 , G06T1/60 , G09G5/001 , G09G5/363 , G09G2360/08 , Y02D10/24
Abstract: One embodiment may include media circuits, an application processor, a direct memory access circuit (DMA), and a media managing circuit. The application processor may issue media commands into a queue. The media managing circuit may retrieve a first media command, set the DMA to copy data associated with the first media command to the first media circuit, and send the first media command to the first media circuit. While the first media command is being executed, the media managing circuit may also retrieve a second media command, determine that the second media command utilizes data that is dependent on a completion of the first media command, and set the DMA to copy data from the first media circuit to the second media circuit. After the first media command has been completed, the media managing circuit may also send the second media command to the second media circuit.
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公开(公告)号：US09653079B2
公开(公告)日：2017-05-16
申请号：US14621093
申请日：2015-02-12
Applicant: Apple Inc.
Inventor： Manu Gulati , Gilbert H. Herbeck , Alexei E. Kosut , Girault W. Jones , Timothy J. Millet
CPC classification number: G10L15/28 , G10L15/08 , G10L15/22 , G10L2015/088 , G10L2015/223
Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.
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公开(公告)号：US09632137B2
公开(公告)日：2017-04-25
申请号：US14693116
申请日：2015-04-22
Applicant: Apple Inc.
Inventor： James D. Ramsay , Manu Gulati , Mitchell Palmer Lichtenberg, Jr.
IPC: G06F11/00 , G01R31/317 , G06F11/22
CPC classification number: G01R31/31705 , G06F11/2221
Abstract: An integrated circuit (IC) having a bridge for interfacing a debugger and method of operating the same is provided. In one embodiment, an IC includes a debug control circuit and a debug interface block (DIB) implemented thereon. The DIB is coupled to the debug control circuit. The IC also includes an interface for a debugger and a number of interfaces for external circuits, each of the interfaces being coupled to the debug control circuit. The debug control circuit may function as a bridge for coupling an external debugger to the DIB and to external circuits coupled to the IC through corresponding ones of the interfaces. The debug control circuit may establish a connection between the debugger and one of the external circuits. Communications between the debugger and the external circuit may be conducted while bypassing the DIB.
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