公开(公告)号：US20190139708A1

公开(公告)日：2019-05-09

申请号：US15804463

申请日：2017-11-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chi-Chang LEE ,  Wen-Long LU

IPC: H01G4/30 ,  H01G4/10 ,  H01G4/008 ,  H01G4/012 ,  H01G4/228

CPC classification number: H01G4/30 ,  H01G4/008 ,  H01G4/0085 ,  H01G4/012 ,  H01G4/10 ,  H01G4/1209 ,  H01G4/1218 ,  H01G4/224 ,  H01G4/228 ,  H01G4/232

Abstract: A capacitor structure includes a first conductive layer, a first insulation layer, a first dielectric layer and a second conductive layer. The first conductive layer includes a first conductive material. The first insulation layer is disposed adjacent to the first conductive layer in a same plane as the first conductive layer. The first dielectric layer is on the first conductive layer and the first insulation layer. The second conductive layer is on the first dielectric layer and includes a second conductive material. The first conductive material is different from the second conductive material.

公开(公告)号：US20190103227A1

公开(公告)日：2019-04-04

申请号：US15721263

申请日：2017-09-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long LU ,  Chi-Chang LEE

IPC: H01G4/33 ,  H01G4/12 ,  H01G4/38 ,  H01G4/228 ,  H01G4/224 ,  H01L27/01 ,  H01L49/02 ,  H01G4/012

CPC classification number: H01G4/33 ,  H01G4/012 ,  H01G4/1254 ,  H01G4/224 ,  H01G4/228 ,  H01G4/385 ,  H01L27/016 ,  H01L28/91

Abstract: A capacitor structure is disclosed. The capacitor structure includes a substrate, and a first electrode disposed on the substrate, the first electrode including a conductive layer, a first conductive post electrically connected to the conductive layer and a second conductive post electrically connected to the conductive layer. The capacitor structure further includes a planarization layer disposed on and covering the first electrode, the planarization layer disposed in a space between the first conductive post and the second conductive post, a first dielectric layer disposed on the planarization layer and in the space between the first conductive post and the second conductive post, and a second electrode disposed on the first dielectric layer.

公开(公告)号：US20190067142A1

公开(公告)日：2019-02-28

申请号：US15685869

申请日：2017-08-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Jen-Kuang FANG ,  Wen-Long LU

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  B23K3/06 ,  H01L23/00

Abstract: A semiconductor package device comprises a first dielectric layer, a first conductive pad and a first conductive element. The first dielectric layer has a first surface and a second surface opposite to the first surface. The first dielectric layer defines a first opening tapered from the first surface toward the second surface. The first conductive pad is within the first opening and adjacent to the second surface of the first dielectric layer. At least a portion of the first conductive element is within the first opening. The first conductive element is engaged with (e.g., abuts) a sidewall of the first opening, the first conductive element having a first surface facing toward the first conductive pad, wherein the first surface of the first conductive element is spaced apart from the first conductive pad.

公开(公告)号：US20180342473A1

公开(公告)日：2018-11-29

申请号：US15605897

申请日：2017-05-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long LU ,  Yuan-Feng CHIANG ,  Tsung-Tang TSAI

IPC: H01L23/00

Abstract: A via structure includes a base material, a first dielectric layer and a second dielectric layer. The base material includes a first surface and a second surface opposite to the first surface, and defines at least one through hole. The first dielectric layer is disposed on the first surface of the base material and includes a gradient surface exposed in the through hole of the base material. The second dielectric layer is disposed on the gradient surface of first dielectric layer.

公开(公告)号：US20180138115A1

公开(公告)日：2018-05-17

申请号：US15349957

申请日：2016-11-11

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long LU

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66

CPC classification number: H01L24/11 ,  H01L21/486 ,  H01L21/561 ,  H01L21/6835 ,  H01L22/14 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L2021/6006 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2224/81 ,  H01L2224/83

Abstract: A semiconductor package structure includes a dielectric structure defining a plurality of through holes, wherein each of the through holes includes a first portion defined by a first sidewall portion and a second portion defined by a second sidewall portion substantially coplanar with the first sidewall portion. The semiconductor package structure further includes a redistribution layer structure disposed on a first surface of the dielectric structure, including a plurality of conductive pads and a plurality of first conductive traces, wherein each of the conductive pads is disposed in a respective through hole, and a sidewall of the conductive pad contacts the first sidewall portion of the through hole, a semiconductor die electrically connected to the redistribution layer structure, and a plurality of conductive structures each disposed on a respective one of the conductive pads and disposed in the second portion of the through hole, wherein a sidewall of the conductive structure and the second sidewall portion of the through hole define a gap.

公开(公告)号：US20180122750A1

公开(公告)日：2018-05-03

申请号：US15791979

申请日：2017-10-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long LU

IPC: H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L21/54 ,  H01L21/48 ,  H01L25/10 ,  H01L23/31 ,  H01L23/18 ,  H01L23/498

Abstract: Various embodiments relate to a semiconductor package structure. The semiconductor package structure includes a first chip having a first surface and a second surface opposite the first surface. The semiconductor package structure further includes a supporter surrounding an edge of the first chip, and the supporter includes a recessed portion. The semiconductor package structure further includes a conductive layer disposed over the first surface of the first chip and electrically connected to the first chip. The semiconductor package structure further includes an insulation layer disposed over the first surface of the first chip. The semiconductor package structure further includes an encapsulant between the first chip and the supporter and surrounding at least the edge of the first chip.

公开(公告)号：US20180076122A1

公开(公告)日：2018-03-15

申请号：US15818337

申请日：2017-11-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long LU ,  Min Lung HUANG

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3157 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A semiconductor process includes: (a) attaching a metal layer on a carrier; (b) removing a portion of the metal layer to form a through hole and at least one metal via, wherein the at least one metal via is disposed in the through hole, and the at least one metal via is separated from a side wall of the through hole by a space; and (c) forming a redistribution layer on the metal layer, wherein the redistribution layer is electrically connected to the at least one metal via.

公开(公告)号：US20170207151A1

公开(公告)日：2017-07-20

申请号：US14995572

申请日：2016-01-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long LU ,  Chi-Chang LEE ,  Wei-Min HSIAO ,  Yuan-Feng CHIANG

IPC: H01L23/495 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49572 ,  H01L21/4825 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/145 ,  H01L23/147 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49575 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/15313 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2224/83 ,  H01L2224/81

Abstract: A semiconductor package structure includes a conductive structure, at least two semiconductor elements and an encapsulant. The conductive structure has a first surface and a second surface opposite the first surface. The semiconductor elements are disposed on and electrically connected to the first surface of the conductive structure. The encapsulant covers the semiconductor elements and the first surface of the conductive structure. The encapsulant has a width ‘L’ and defines at least one notch portion. A minimum distance ‘d’ is between a bottom surface of the notch portion and the second surface of the conductive structure. The encapsulant has a Young's modulus ‘E’ and a rupture strength ‘Sr’, and L/(K×d)>E/Sr, wherein ‘K’ is a stress concentration factor with a value of greater than 1.2.