公开(公告)号：US10529664B2

公开(公告)日：2020-01-07

申请号：US15985472

申请日：2018-05-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long Lu

IPC: H01L23/532 ,  H01L23/00

Abstract: An electronic device includes a first substrate, a first conductor, a first insulation layer, a second substrate, a second conductor, a second insulation layer. The first substrate has a first surface. The first conductor is disposed on the first surface of the first substrate. The first insulation layer is on the first conductor. The second substrate has a second surface facing toward the first surface of the first substrate. The second conductor is disposed on the second surface of the second substrate. The second insulation layer is on the second conductor. The first insulation layer is in contact with a sidewall of the second conductor. The second insulation layer is in contact with a sidewall of the first conductor. A coefficient of thermal expansion (CTE) of the first insulation layer is greater than a CTE of the first conductor.

公开(公告)号：US10515889B2

公开(公告)日：2019-12-24

申请号：US15783353

申请日：2017-10-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long Lu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48

Abstract: A semiconductor package device includes an interconnection structure, an electronic component, a package body and an electrical contact. The dielectric layer has a top surface and a bottom surface. The dielectric layer defines a cavity extending from the bottom surface into the dielectric layer. A patterned conductive layer is disposed on the top surface of the dielectric layer. The conductive pad is at least partially disposed within the cavity and electrically connected to the patterned conductive layer. The conductive pad includes a first metal layer and a second metal layer. The second metal layer is disposed on the first metal layer and extends along a lateral surface of the first metal layer. The electronic component is electrically connected to the patterned conductive layer. The package body covers the electronic component and the patterned conductive layer. The electrical contact is electrically connected to the conductive pad.

公开(公告)号：US10418314B2

公开(公告)日：2019-09-17

申请号：US15801108

申请日：2017-11-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long Lu

IPC: H01L23/12 ,  H01L21/00 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/528 ,  H01L23/48 ,  H01L23/522

Abstract: At least some embodiments of the present disclosure relate to a substrate for packaging a semiconductor device. The substrate includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, a second patterned conductive layer adjacent to the second surface of the first dielectric layer and electrically connected to the first patterned conductive layer, and an external connection pad tapered from a top surface to a bottom surface. The second patterned conductive layer includes a pad and a trace adjacent to the pad. The external connection pad is disposed on the pad of the second patterned conductive layer. A bottom width of the external connection pad is greater than or equal to a width of the pad of the second patterned conductive layer.

公开(公告)号：US10276480B1

公开(公告)日：2019-04-30

申请号：US15795201

申请日：2017-10-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long Lu

IPC: H01L21/44 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56

Abstract: A substrate structure includes a dielectric layer, a first circuit layer, a second circuit layer and at least one conductive pillar. The dielectric layer has a first surface and a second surface opposite to the first surface. The first circuit layer is disposed adjacent to the first surface of the dielectric layer. The second circuit layer is disposed adjacent to the second surface of the dielectric layer and electrically connected to the first circuit layer. The second circuit layer includes a plurality of pads and at least one trace disposed between two adjacent pads of the plurality of pads. The at least one conductive pillar is tapered toward the second circuit layer and disposed on one of the pads. A portion of the second surface of the dielectric layer is exposed from the second surface layer.

公开(公告)号：US10217712B2

公开(公告)日：2019-02-26

申请号：US15382594

申请日：2016-12-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long Lu

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/48 ,  H01L21/48

Abstract: A semiconductor package includes a substrate, a dielectric layer, at least one conductive pillar and an electrical device. The dielectric layer is disposed on the substrate and defines at least one through hole corresponding to the respective first pad of the substrate. The conductive pillar is disposed in the respective through hole. The conductive pillar includes a body portion and a cap portion. The body portion is physically connected to the cap portion, and the cap portion is electrically connected to the first pad. A maximum width of the cap portion is greater than a maximum width of the body portion. The electrical device is disposed on the dielectric layer and electrically connected to the body portion of the conductive pillar.

公开(公告)号：US09929078B2

公开(公告)日：2018-03-27

申请号：US14995572

申请日：2016-01-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long Lu ,  Chi-Chang Lee ,  Wei-Min Hsiao ,  Yuan-Feng Chiang

IPC: H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/29

CPC classification number: H01L23/49572 ,  H01L21/4825 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/145 ,  H01L23/147 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49575 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/15313 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2224/83 ,  H01L2224/81

Abstract: A semiconductor package structure includes a conductive structure, at least two semiconductor elements and an encapsulant. The conductive structure has a first surface and a second surface opposite the first surface. The semiconductor elements are disposed on and electrically connected to the first surface of the conductive structure. The encapsulant covers the semiconductor elements and the first surface of the conductive structure. The encapsulant has a width ‘L’ and defines at least one notch portion. A minimum distance ‘d’ is between a bottom surface of the notch portion and the second surface of the conductive structure. The encapsulant has a Young's modulus ‘E’ and a rupture strength ‘Sr’, and L/(K×d)>E/Sr, wherein ‘K’ is a stress concentration factor with a value of greater than 1.2.

公开(公告)号：US09852971B1

公开(公告)日：2017-12-26

申请号：US15178066

申请日：2016-06-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long Lu ,  Min Lung Huang

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/3157 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/181 ,  H01L2924/00012

Abstract: An interposer includes an interconnection structure and a redistribution layer. The interconnection structure includes a metal layer, at least one metal via and an isolation material. The metal layer defines at least one through hole having a side wall. The at least one metal via is disposed in the through hole. A space is defined between the at least one metal via and the side wall of the through hole, and the isolation material fills the space. The redistribution layer is disposed on a surface of the interconnection structure and is electrically connected to the metal via.

公开(公告)号：US09831195B1

公开(公告)日：2017-11-28

申请号：US15338176

申请日：2016-10-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long Lu

IPC: H01L23/18 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L21/54 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/54 ,  H01L21/565 ,  H01L23/16 ,  H01L23/18 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/08 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/24137 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/83

Abstract: Various embodiments relate to a semiconductor package structure. The semiconductor package structure includes a first chip having a first surface and a second surface opposite the first surface. The semiconductor package structure further includes a supporter surrounding an edge of the first chip. The semiconductor package structure further includes a conductive layer disposed over the first surface of the first chip and electrically connected to the first chip. The semiconductor package structure further includes an insulation layer disposed over the first surface of the first chip, wherein the insulation layer extends toward and overlaps the supporter in a vertical projection direction. The semiconductor package structure further includes an encapsulant between the first chip and the supporter and surrounding at least the edge of the first chip.