公开(公告)号：US20180324357A1

公开(公告)日：2018-11-08

申请号：US16019906

申请日：2018-06-27

Applicant: Apple Inc.

Inventor： D. Amnon Silverstein ,  Shun Wai Go ,  Suk Hwan Lim ,  Timothy J. Millet ,  Ting Chen ,  Bin Ni

IPC: H04N5/232 ,  H04N9/87 ,  H04N7/01 ,  H04N1/21

CPC classification number: H04N5/23245 ,  H04N1/212 ,  H04N5/23216 ,  H04N5/23232 ,  H04N5/23293 ,  H04N7/0122 ,  H04N9/87

Abstract: In an embodiment, an electronic device may be configured to capture still frames during video capture but may capture the still frames in the 4×3 aspect ratio and at higher resolution than the 16×9 aspect ratio video frames. The device may interleave high resolution, 4×3 frames and lower resolution 16×9 frames in the video sequence, and may capture the nearest higher resolution, 4×3 frame when the user indicates the capture of a still frame. Alternatively, the device may display 16×9 frames in the video sequence, and then expand to 4×3 frames when a shutter button is pressed. The device may capture the still frame and return to the 16×9 video frames responsive to a release of the shutter button.

公开(公告)号：US20170213557A1

公开(公告)日：2017-07-27

申请号：US15482142

申请日：2017-04-07

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Gilbert H. Herbeck ,  Alexei E. Kosut ,  Girault W. Jones ,  Timothy J. Millet

IPC: G10L15/28 ,  G10L15/08 ,  G10L15/22

CPC classification number: G10L15/28 ,  G10L15/08 ,  G10L15/22 ,  G10L2015/088 ,  G10L2015/223

Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.

公开(公告)号：US09699481B2

公开(公告)日：2017-07-04

申请号：US13651181

申请日：2012-10-12

Applicant: Apple Inc.

Inventor： Haitao Guo ,  Sally Fung ,  Timothy J. Millet

IPC: H04N7/12 ,  H04N19/86

CPC classification number: H04N19/86

Abstract: A technique is provided for processing decoded video data to mask visual compression artifacts resulting from video compression. In accordance with this technique, a hardware block is provided for generating and adding random noise to the decoded video stream. In one embodiment, a random number is generated for each pixel of the decoded video data and compared against one or more threshold values to determine a threshold range. In such an embodiment, a noise addend value is selected based upon the threshold comparison and summed with the current pixel. While the present technique may not eliminate the compression artifacts, the addition of random noise renders the compression artifacts less noticeable to the human eye and, therefore, more aesthetically pleasing to a viewer.

公开(公告)号：US20170134655A1

公开(公告)日：2017-05-11

申请号：US15414866

申请日：2017-01-25

Applicant: Apple Inc.

Inventor： D. Amnon Silverstein ,  Shun Wai Go ,  Suk Hwan Lim ,  Timothy J. Millet ,  Ting Chen ,  Bin Ni

IPC: H04N5/232

CPC classification number: H04N5/23245 ,  H04N1/212 ,  H04N5/23216 ,  H04N5/23232 ,  H04N5/23293 ,  H04N7/0122 ,  H04N9/87

Abstract: In an embodiment, an electronic device may be configured to capture still frames during video capture, but may capture the still frames in the 4×3 aspect ratio and at higher resolution than the 16×9 aspect ratio video frames. The device may interleave high resolution, 4×3 frames and lower resolution 16×9 frames in the video sequence, and may capture the nearest higher resolution, 4×3 frame when the user indicates the capture of a still frame. Alternatively, the device may display 16×9 frames in the video sequence, and then expand to 4×3 frames when a shutter button is pressed. The device may capture the still frame and return to the 16×9 video frames responsive to a release of the shutter button.

公开(公告)号：US20170132131A1

公开(公告)日：2017-05-11

申请号：US15352693

申请日：2016-11-16

Applicant: Apple Inc.

Inventor： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

IPC: G06F12/0846 ,  G06F12/0853

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0638 ,  G06F3/0673 ,  G06F12/0802 ,  G06F12/0831 ,  G06F12/0848 ,  G06F12/0853 ,  G06F12/0864 ,  G06F12/0877 ,  G06F12/125 ,  G06F2212/1021 ,  G06F2212/2515 ,  G06F2212/282 ,  G06F2212/601 ,  G06F2212/62 ,  Y02D10/13

Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

公开(公告)号：US20170039672A1

公开(公告)日：2017-02-09

申请号：US14816508

申请日：2015-08-03

Applicant: Apple Inc.

Inventor： Timothy J. Millet ,  Manu Gulati ,  Arthur L. Spence ,  Gurjeet S. Saund ,  Robert P. Esser

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F9/4893 ,  G06F9/52 ,  G06T1/60 ,  G09G5/001 ,  G09G5/363 ,  G09G2360/08 ,  Y02D10/24

Abstract: An embodiment of a system may include a plurality of media units, a processor, and circuitry. Each media unit may be configured to execute one or more commands to process a display image. The processor may be configured to store a plurality of media processing commands in a queue. The circuitry may be configured to retrieve a first media processing command from the queue and send the first media processing command to a first media unit. The circuitry may also be configured to retrieve a second media processing from the queue and send the second media processing command to a second media unit in response to receiving an interrupt from the first media unit. The circuitry may then copy data from the first media unit to the second media unit in response to receiving the interrupt from the first media unit.

Abstract translation: 系统的实施例可以包括多个媒体单元，处理器和电路。 每个媒体单元可以被配置为执行一个或多个命令来处理显示图像。 处理器可以被配置为在队列中存储多个媒体处理命令。 电路可以被配置为从队列检索第一媒体处理命令，并将第一媒体处理命令发送到第一媒体单元。 电路还可以被配置为响应于从第一媒体单元接收到中断而从队列中检索第二媒体处理并将第二媒体处理命令发送到第二媒体单元。 响应于接收到来自第一媒体单元的中断，电路可以将数据从第一媒体单元复制到第二媒体单元。

公开(公告)号：US20160065973A1

公开(公告)日：2016-03-03

申请号：US14472119

申请日：2014-08-28

Applicant: APPLE INC.

Inventor： Guy Cote ,  Joseph P. Bratt ,  Timothy J. Millet ,  Shing I. Kong ,  Joseph J. Cheng

IPC: H04N19/186 ,  H04N19/423 ,  H04N19/172 ,  H04N19/176

CPC classification number: H04N19/186 ,  G06F12/00 ,  G06F12/0207 ,  G06F12/0862 ,  G06F12/121 ,  G06F2212/1024 ,  G06F2212/455 ,  G06F2212/6024 ,  G06F2212/6026 ,  G06T1/60 ,  H04N19/127 ,  H04N19/172 ,  H04N19/176 ,  H04N19/423 ,  H04N19/433 ,  H04N19/439

Abstract: Methods and apparatus for caching reference data in a block processing pipeline. A cache may be implemented to which reference data corresponding to motion vectors for blocks being processed in the pipeline may be prefetched from memory. Prefetches for the motion vectors may be initiated one or more stages prior to a processing stage. Cache tags for the cache may be defined by the motion vectors. When a motion vector is received, the tags can be checked to determine if there are cache block(s) corresponding to the vector (cache hits) in the cache. Upon a cache miss, a cache block in the cache is selected according to a replacement policy, the respective tag is updated, and a prefetch (e.g., via DMA) for the respective reference data is issued.

Abstract translation: 在块处理流水线中缓存参考数据的方法和装置。 可以实现缓存，其可以从存储器预取哪个对应于在流水线中处理的块的运动矢量的参考数据。 可以在处理阶段之前一个或多个阶段启动用于运动矢量的预取。 高速缓存的缓存标签可以由运动向量定义。 当接收到运动矢量时，可以检查标签以确定是否存在与缓存中的向量（高速缓存命中）相对应的高速缓存块。 在缓存未命中时，根据替换策略来选择高速缓存中的高速缓存块，相应的标签被更新，并且发出用于各个参考数据的预取（例如，经由DMA）。

公开(公告)号：US20150278134A1

公开(公告)日：2015-10-01

申请号：US14709336

申请日：2015-05-11

Applicant: Apple Inc.

Inventor： David G. Conroy ,  Timothy J. Millet ,  Joseph P. Bratt

IPC: G06F13/34 ,  G06F13/16

CPC classification number: G06F13/34 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F1/3287 ,  G06F13/1673 ,  G06F13/28 ,  Y02D10/126 ,  Y02D10/151 ,  Y02D10/171

Abstract: A method and system is disclosed for accessing I/O and memory devices utilizing a DMA controller. Each device may be connected to the DMA controller through an individual channel. Clocking circuitry in the DMA may allow the DMA controller to send signals to each device at a prescribed frequency. Furthermore, the DMA controller is capable of activating and deactivating a channel clock, used in sending signals to the devices, based on the operational status of the individual devices. The DMA controller is also capable of tuning the channel clock dependant on the capabilities of any active devices. In this manner, the amount of bandwidth used during a DMA data transfer can be tailored to the specific requirements of the devices involved with the data transfer.

公开(公告)号：US08963587B2

公开(公告)日：2015-02-24

申请号：US13893926

申请日：2013-05-14

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Raman S. Thiara ,  Shane J. Keil ,  Timothy J. Millet

IPC: H03K21/00

CPC classification number: H03K5/15013 ,  G06F1/04 ,  G06F1/08

Abstract: Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block.

Abstract translation: 公开了可以允许改变耦合到集成电路内的功能块的时钟的频率的装置的实施例。 该装置可以包括多个时钟分频器和多路复用电路。 多个时钟分频器中的每一个可以将基本时钟信号的频率划分为多个除数中的相应一个。 多路复用电路可以被配置为接收多个选择信号，根据接收到的选择信号选择多个时钟分频器之一的输出，并将多个时钟分频器的选择输出耦合到功能块。

公开(公告)号：US20140340130A1

公开(公告)日：2014-11-20

申请号：US13893926

申请日：2013-05-14

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Raman S. Thiara ,  Shane J. Keil ,  Timothy J. Millet

IPC: H03K3/02

CPC classification number: H03K5/15013 ,  G06F1/04 ,  G06F1/08

Abstract: Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block.

Abstract translation: 公开了可以允许改变耦合到集成电路内的功能块的时钟的频率的装置的实施例。 该装置可以包括多个时钟分频器和多路复用电路。 多个时钟分频器中的每一个可以将基本时钟信号的频率划分为多个除数中的相应一个。 多路复用电路可以被配置为接收多个选择信号，根据接收到的选择信号选择多个时钟分频器之一的输出，并将多个时钟分频器的选择输出耦合到功能块。