摘要:
A multi-junction photovoltaic device includes a germanium layer having pyramidal shapes with (111) facets exposed to form a textured surface. A first p-n junction is formed on or over the textured surface. Another p-n junction is formed over the first p-n junction and following the textured surface.
摘要:
An SOI substrate including a buried insulator layer positioned between a base substrate and a top semiconductor active layer is first provided. A semiconductor device can then be formed on and/or within a portion of the top semiconductor active layer. A bottommost surface of the buried insulator layer which is opposite a topmost surface of the buried insulator layer that forms an interface with the top semiconductor active layer can be then exposed. Ions can then be implanted through the bottommost surface of the buried insulator layer and into a portion of the buried insulator layer. The ions are implanted at energy ranges that do not disturb the buried insulator layer/top semiconductor active layer interface, while leaving a relatively thin portion of the buried insulator layer near the buried insulator layer/top semiconductor active layer interface intact.
摘要:
A solar cell having n-type and p-type interdigitated back contacts (IBCs), which cover the entire back surface of the absorber layer. The spatial separation of the IBCs is in a direction perpendicular to the back surface, thus providing borderless contacts having a zero-footprint separation. As the contacts are on the back, photons incident on the cell's front surface can be absorbed without any shadowing.
摘要:
A method cleaving a semiconductor material that includes providing a germanium substrate having a germanium and tin alloy layer is present therein. A stressor layer is deposited on a surface of the germanium substrate. A stress from the stressor layer is applied to the germanium substrate, in which the stress cleaves the germanium substrate to provide a cleaved surface. The cleaved surface of the germanium substrate is then selective to the germanium and tin alloy layer of the germanium substrate. In another embodiment, the germanium and tin alloy layer may function as a fracture plane during a spalling method.
摘要:
Solar cell structures that have improved carrier collection efficiencies at a heterointerface are provided by low temperature epitaxial growth of silicon on a III-V base. Additionally, a solar cell structure having improved open circuit voltage includes a shallow junction III-V emitter formed by epitaxy or diffusion followed by the epitaxy of SixGe1-x passivated by amorphous SiyGe1-y:H.
摘要:
A method cleaving a semiconductor material that includes providing a germanium substrate having a germanium and tin alloy layer is present therein. A stressor layer is deposited on a surface of the germanium substrate. A stress from the stressor layer is applied to the germanium substrate, in which the stress cleaves the germanium substrate to provide a cleaved surface. The cleaved surface of the germanium substrate is then selective to the germanium and tin alloy layer of the germanium substrate. In another embodiment, the germanium and tin alloy layer may function as a fracture plane during a spalling method.
摘要:
A solar cell having n-type and p-type interdigitated back contacts (IBCs), which cover the entire back surface of the absorber layer. The spatial separation of the IBCs is in a direction perpendicular to the back surface, thus providing borderless contacts having a zero-footprint separation. As the contacts are on the back, photons incident on the cell's front surface can be absorbed without any shadowing.
摘要:
An autonomous integrated circuit (IC) includes a solar cell formed on a bottom substrate of a silicon-on-insulator (SOI) substrate as a handle substrate; an insulating layer of the SOI substrate located on top of the solar cell; and a device layer formed on a top semiconductor layer of the SOI substrate located on top of the insulating layer, wherein a top contact of the device layer is electrically connected to a bottom contact of the solar cell such that the solar cell is enabled to power the device layer.
摘要:
Methods for detecting the physical layout of an integrated circuit are provided. The methods of the present disclosure allow large area imaging of the circuit layout without requiring tedious sample preparation techniques. The imaging can be performed utilizing low-energy beam techniques such as scanning electron microscopy; however, more sophisticated imaging techniques can also be employed. In the methods of the present disclosure, spalling is used to remove a portion of a semiconductor layer including at least one semiconductor device formed thereon or therein from a base substrate. In some cases, a buried insulator layer that is located beneath a semiconductor layer including the at least one semiconductor device can be completely or partially removed. In some cases, the semiconductor layer including the at least one semiconductor device can be thinned. The methods improve the detection quality that the buried insulator layer and a thick semiconductor layer can reduce.
摘要:
An SOI substrate including a buried insulator layer positioned between a base substrate and a top semiconductor active layer is first provided. A semiconductor device can then be formed on and/or within a portion of the top semiconductor active layer. A bottommost surface of the buried insulator layer which is opposite a topmost surface of the buried insulator layer that forms an interface with the top semiconductor active layer can be then exposed. Ions can then be implanted through the bottommost surface of the buried insulator layer and into a portion of the buried insulator layer. The ions are implanted at energy ranges that do not disturb the buried insulator layer/top semiconductor active layer interface, while leaving a relatively thin portion of the buried insulator layer near the buried insulator layer/top semiconductor active layer interface intact.