公开(公告)号：US10276659B2

公开(公告)日：2019-04-30

申请号：US15992431

申请日：2018-05-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chun-Chen Yeh ,  Kangguo Cheng ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: A vertical transistor device includes a vertically-oriented channel semiconductor (VOCS) structure positioned above a substrate and a first bottom spacer positioned above the substrate adjacent the VOCS structure. The first bottom spacer extends around less than an entirety of a perimeter of the VOCS structure. A gate structure is positioned around the VOCS structure. Only a portion of the gate structure is positioned vertically above the first bottom spacer so as to thereby define an air gap that is positioned under the gate structure. The air gap extends around a majority of a perimeter of the VOCS structure and a second bottom spacer positioned above the substrate. An upper portion of the second bottom spacer contacts a material formed around the VOCS structure so as to seal the air gap. The second bottom spacer has a vertical thickness that is greater than a vertical thickness of the air gap.

公开(公告)号：US20190103319A1

公开(公告)日：2019-04-04

申请号：US15723472

申请日：2017-10-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Jianwei Peng ,  Wei Hong ,  Yanping Shen ,  Yongjun Shi ,  Hui Zang ,  Ruilong Xie ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/088

Abstract: Disclosed is a method of forming a structure with multiple vertical field effect transistors (VFETs). In the method, lower source/drain regions are formed on a substrate such that semiconductor fins extend vertically above the lower source/drain regions. Lower spacers are formed on the lower source/drain regions and positioned laterally adjacent to the semiconductor fins. Gates, having co-planar top surfaces, are formed on the lower spacers and positioned laterally adjacent to the semiconductor fins. However, process steps are performed prior to gate formation to ensure that the top surfaces of the lower source/drain region and lower spacer of a first VFET are below the levels of the top surfaces of the lower source/drain region and lower spacer, respectively, of a second VFET. As a result, the first VFET will have a longer gate, higher threshold voltage and lower switching speed. Also disclosed is the structure formed according to the method.

公开(公告)号：US10249538B1

公开(公告)日：2019-04-02

申请号：US15723472

申请日：2017-10-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Jianwei Peng ,  Wei Hong ,  Yanping Shen ,  Yongjun Shi ,  Hui Zang ,  Ruilong Xie ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/3213 ,  H01L21/311

Abstract: Disclosed is a method of forming a structure with multiple vertical field effect transistors (VFETs). In the method, lower source/drain regions are formed on a substrate such that semiconductor fins extend vertically above the lower source/drain regions. Lower spacers are formed on the lower source/drain regions and positioned laterally adjacent to the semiconductor fins. Gates, having co-planar top surfaces, are formed on the lower spacers and positioned laterally adjacent to the semiconductor fins. However, process steps are performed prior to gate formation to ensure that the top surfaces of the lower source/drain region and lower spacer of a first VFET are below the levels of the top surfaces of the lower source/drain region and lower spacer, respectively, of a second VFET. As a result, the first VFET will have a longer gate, higher threshold voltage and lower switching speed. Also disclosed is the structure formed according to the method.

公开(公告)号：US10217869B2

公开(公告)日：2019-02-26

申请号：US15936149

申请日：2018-03-26

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L21/02 ,  H01L21/321 ,  H01L29/423 ,  H01L21/28 ,  H01L29/786

Abstract: A semiconductor structure includes a substrate, and a replacement metal gate (RMG) structure is attached to the substrate. The RMG structure includes a lower portion and an upper tapered portion. A source junction is disposed on the substrate and attached to a first low-k spacer portion. A drain junction is disposed on the substrate and attached to a second low-k spacer portion. A first oxide layer is disposed on the source junction, and attached to the first low-k spacer portion. A second oxide layer is disposed on the drain junction, and attached to the second low-k spacer portion. A cap layer is disposed on a top surface layer of the RMG structure and attached to the first oxide layer and the second oxide layer.

公开(公告)号：US20180308930A1

公开(公告)日：2018-10-25

申请号：US15992431

申请日：2018-05-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chun-Chen Yeh ,  Kangguo Cheng ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

Abstract: A vertical transistor device includes a vertically-oriented channel semiconductor (VOCS) structure positioned above a substrate and a first bottom spacer positioned above the substrate adjacent the VOCS structure. The first bottom spacer extends around less than an entirety of a perimeter of the VOCS structure. A gate structure is positioned around the VOCS structure. Only a portion of the gate structure is positioned vertically above the first bottom spacer so as to thereby define an air gap that is positioned under the gate structure. The air gap extends around a majority of a perimeter of the VOCS structure and a second bottom spacer positioned above the substrate. An upper portion of the second bottom spacer contacts a material formed around the VOCS structure so as to seal the air gap. The second bottom spacer has a vertical thickness that is greater than a vertical thickness of the air gap.

公开(公告)号：US10096674B2

公开(公告)日：2018-10-09

申请号：US15717336

申请日：2017-09-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/092

Abstract: A method of making a nanowire device includes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.

公开(公告)号：US10037919B1

公开(公告)日：2018-07-31

申请号：US15609603

申请日：2017-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chun-Chen Yeh ,  Kangguo Cheng ,  Tenko Yamashita

IPC: H01L21/336 ,  H01L21/8222 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823487 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

Abstract: A structure and method of making a semiconductor device includes a single-gated vertical field effect transistor (VFET), that has a first fin on a first bottom source/drain region, a gate of a first work force metal (WFM) surrounding the first fin, and a single gate contact connected to the first WFM. Also included is a double-gated VFET, that has a second fin on a second bottom source/drain region, a first gate of the first WFM disposed on a first side of the second fin, a second wider gate of a second WFM disposed on a second side of the second fin, a first gate contact contacting the first narrow gate, and a second gate contact contacting the second wider gate of the second WFM on the second side.

公开(公告)号：US10032912B2

公开(公告)日：2018-07-24

申请号：US14588221

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Pierre Morin ,  Kangguo Cheng ,  Jody Fronheiser ,  Xiuyu Cai ,  Juntao Li ,  Shogo Mochizuki ,  Ruilong Xie ,  Hong He ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

Abstract: A modified silicon substrate having a substantially defect-free strain relaxed buffer layer of SiGe is suitable for use as a foundation on which to construct a high performance CMOS FinFET device. The substantially defect-free SiGe strain-relaxed buffer layer can be formed by making cuts in, or segmenting, a strained epitaxial film, causing edges of the film segments to experience an elastic strain relaxation. When the segments are small enough, the overall film is relaxed so that the film is substantially without dislocation defects. Once the substantially defect-free strain-relaxed buffer layer is formed, strained channel layers can be grown epitaxially from the relaxed SRB layer. The strained channel layers are then patterned to create fins for a FinFET device. In one embodiment, dual strained channel layers are formed—a tensilely strained layer for NFET devices, and a compressively strained layer for PFET devices.

公开(公告)号：US20180204796A1

公开(公告)日：2018-07-19

申请号：US15408883

申请日：2017-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Geng Wang ,  Kangguo Cheng ,  Chengwen Pei ,  Juntao Li

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/822 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5223 ,  H01L21/76805 ,  H01L21/8221 ,  H01L23/5226 ,  H01L23/5283 ,  H01L28/60

Abstract: Various embodiments include three-dimensional (3D) integrated circuit (IC) structures and methods of forming such structures. In some cases, a 3D IC structure includes: a substrate; a first set of transistors overlying the substrate; a first inter-level dielectric (ILD) overlying the first set of transistors and the substrate; a dielectric overlying the first ILD; a semiconductor layer overlying the dielectric; a second set of transistors overlying the semiconductor layer; a capacitor embedded within the dielectric; and a first contact extending through the semiconductor layer and the dielectric to contact one layer of the capacitor, and a second contact extending through the semiconductor layer and the dielectric to contact a second, distinct layer of the capacitor.

公开(公告)号：US10014370B1

公开(公告)日：2018-07-03

申请号：US15491420

申请日：2017-04-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chun-Chen Yeh ,  Kangguo Cheng ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

Abstract: One illustrative method disclosed herein includes, among other things, forming an initial bottom spacer above a semiconductor substrate and adjacent a vertically-oriented channel semiconductor (VOCS) structure and forming a gate structure around the VOCS structure and above the initial bottom spacer. In this example, the method also includes performing at least one etching process to remove at least a portion of the initial bottom spacer that is positioned vertically under the gate structure so as to thereby result in the formation of an air gap that is positioned under the gate structure, wherein the air gap extends around at least a majority of a perimeter of the VOCS structure, and forming a replacement bottom spacer above the semiconductor substrate and adjacent the air gap.