公开(公告)号：US09111899B2

公开(公告)日：2015-08-18

申请号：US13613564

申请日：2012-09-13

申请人： Gerald K. Bartley ,  Charles L. Johnson ,  John E. Kelly, III ,  Joseph Kuczynski ,  David R. Motschman ,  Arvind K. Sinha ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

发明人： Gerald K. Bartley ,  Charles L. Johnson ,  John E. Kelly, III ,  Joseph Kuczynski ,  David R. Motschman ,  Arvind K. Sinha ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

IPC分类号： H01L23/48 ,  H01L23/10 ,  H01L23/34 ,  H01L23/367 ,  H01L23/00 ,  H01L21/02 ,  H01L23/373 ,  H01L23/427 ,  H01L25/065

CPC分类号： H01L23/367 ,  H01L21/02656 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/4275 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/95 ,  H01L25/0657 ,  H01L2224/10165 ,  H01L2224/13014 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83909 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

摘要： The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad placed between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip and nanofibers aligned perpendicular to mating surfaces of the first chip and the second chip.

摘要翻译： 具有增强的冷却装置的半导体芯片的芯片堆叠包括具有第一侧上的电路的第一芯片和通过连接器格栅电和机械地耦合到第一芯片的第二芯片。 该装置还包括放置在第一芯片和第二芯片之间的热界面材料垫，其中热界面材料垫包括平行于第一芯片和第二芯片的配合表面排列的纳米纤维，并且纳米纤维垂直于第一芯片和第二芯片的配合表面对齐 芯片和第二芯片。

公开(公告)号：US20130009324A1

公开(公告)日：2013-01-10

申请号：US13618600

申请日：2012-09-14

申请人： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel ,  Patrick Ronald Varekamp

发明人： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel ,  Patrick Ronald Varekamp

IPC分类号： H01L23/522 ,  H01L23/48 ,  G06F17/50

CPC分类号： G06F17/5068 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2224/05599 ,  H01L2224/05099

摘要： An apparatus, program product and method facilitate the design of a multi-layer circuit arrangement incorporating a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers.

摘要翻译： 一种装置，程序产品和方法有助于在多层半导体堆叠中结合通用的标准化层间互连的多层电路装置的设计，以便于布置在半导体管芯堆叠上的功能单元之间的互连和通信。 多层半导体堆叠中的每个电路层需要包括布置在基本上相同的地形位置处的层间界面区域，使得当将这样的电路层设置在其上的半导体管芯堆叠在一起时，电气 布置在每个半导体管芯内的导体彼此对准以提供相对于各个电路层垂直或横向取向的层间总线。

公开(公告)号：US20120187570A1

公开(公告)日：2012-07-26

申请号：US13422606

申请日：2012-03-16

申请人： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel

发明人： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06544

摘要： A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions.

公开(公告)号：US07996641B2

公开(公告)日：2011-08-09

申请号：US12053231

申请日：2008-03-21

申请人： Gerald K. Bartley ,  John M. Borkenhagen ,  Philip Raymond Germann

发明人： Gerald K. Bartley ,  John M. Borkenhagen ,  Philip Raymond Germann

IPC分类号： G06F13/00

CPC分类号： G06F13/4243

摘要： A design structure is provided for a hub for use in a high-capacity memory subsystem in which memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving.

摘要翻译： 提供了一种用于高容量存储器子系统中的集线器的设计结构，其中存储器模块布置在一个或多个集群中，每个集群都附接到相应的集线器，而集线器又连接到存储器控制器。 在集群内，数据被交织，以便每个数据访问命令访问集群的所有模块。 集线器以较低的总线频率与存储器模块通信，但是在多个模块之间分配数据使集群能够保持存储器 - 控制器到集线器总线的复合数据速率。 优选地，存储器系统采用具有双模操作的缓冲存储器芯片，其中之一支持数据被交错的集群配置，并且通信总线以减小的总线宽度和/或减少的总线频率进行操作以匹配交织级别。

公开(公告)号：US20090006706A1

公开(公告)日：2009-01-01

申请号：US12053231

申请日：2008-03-21

申请人： Gerald K. Bartley ,  John M. Borkenhagen ,  Philip Raymond Germann

发明人： Gerald K. Bartley ,  John M. Borkenhagen ,  Philip Raymond Germann

IPC分类号： G06F13/36 ,  G06F12/00

CPC分类号： G06F13/4243

摘要： A design structure is provided for a hub for use in a high-capacity memory subsystem in which memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving

摘要翻译： 提供了一种用于高容量存储器子系统中的集线器的设计结构，其中存储器模块布置在一个或多个集群中，每个集群都附接到相应的集线器，而集线器又连接到存储器控制器。 在集群内，数据被交织，以便每个数据访问命令访问集群的所有模块。 集线器以较低的总线频率与存储器模块通信，但是在多个模块之间分配数据使集群能够保持存储器 - 控制器到集线器总线的复合数据速率。 优选地，存储器系统采用具有双模操作的缓冲存储器芯片，其中之一支持数据被交错的集群配置，并且通信总线以减小的总线宽度和/或减小的总线频率进行操作以匹配交织电平

公开(公告)号：US6084775A

公开(公告)日：2000-07-04

申请号：US207785

申请日：1998-12-09

申请人： Gerald K. Bartley ,  Douglas A. Baska ,  James D. Bielick ,  Matthew A. Butterbaugh ,  Mark K. Hoffmeyer ,  Sukhvinder Singh Kang

发明人： Gerald K. Bartley ,  Douglas A. Baska ,  James D. Bielick ,  Matthew A. Butterbaugh ,  Mark K. Hoffmeyer ,  Sukhvinder Singh Kang

IPC分类号： H01L21/48 ,  H01L23/373 ,  H05K7/20

CPC分类号： H01L23/3735 ,  H01L21/4882 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/14

摘要： Aluminum heatsinks are plated with a solderable layer and are overplated with a solder release layer. The release layer comprises a tin-lead-indium alloy. The heatsinks are mounted on individual IC modules or banks of IC modules that are interconnected to a printed circuit card. A mechanically compliant, thermally conductive adhesive is used to join the heatsinks to the modules. An oxide formed on the release layer readily bonds with the thermally conductive adhesive. In the event that heatsinks need to be removed to repair or rework the modules, local heat may be applied to melt the release layer to remove a heatsink without need for use of significant applied torque and normal forces. Because the release layer has a low melting point that affords easy separation from the adhesive layer, both component delaminations and the partial reflow or melting of solder joints on adjacent components are eliminated from the heatsink removal process.

摘要翻译： 铝散热器镀有可焊层，并用焊料释放层覆盖。 剥离层包括锡 - 铅 - 铟合金。 散热器安装在与印刷电路卡互连的IC模块或集成电路模块组中。 使用机械兼容的导热粘合剂将散热器连接到模块。 形成在剥离层上的氧化物容易与导热粘合剂结合。 在需要去除散热器来修理或重新组装模块的情况下，可以施加局部热量来熔化释放层以除去散热器，而不需要使用显着施加的扭矩和法向力。 由于释放层具有提供与粘合剂层容易分离的低熔点，因此从散热器去除工艺中消除了相邻部件上的焊料接合部分脱模和部分回流或熔化。

公开(公告)号：US5937269A

公开(公告)日：1999-08-10

申请号：US960695

申请日：1997-10-29

申请人： Roy Yu ,  Gerald K. Bartley ,  Peter A. Franklin ,  Carmine J. Mele ,  Arthur G. Merryman ,  John R. Pennacchia ,  Kurt A. Smith ,  Thomas A. Wassick ,  Thomas A. Wayson

发明人： Roy Yu ,  Gerald K. Bartley ,  Peter A. Franklin ,  Carmine J. Mele ,  Arthur G. Merryman ,  John R. Pennacchia ,  Kurt A. Smith ,  Thomas A. Wassick ,  Thomas A. Wayson

IPC分类号： H01L21/66 ,  H05K3/22 ,  H01L21/00

CPC分类号： H01L22/22 ,  H05K3/225 ,  H01L2924/0002

摘要： A Process for graphically assisting the partial repair of defective MCM TF wiring nets. The process comprises the steps of inserting the wiring layer of the thin-film device in a tester, scanning the wiring layer of the thin-film device with the tester, identifying defects in the wiring nets, prioritizing the defects based on a function of each of the defective wiring nets, and repairing the defects based on priority.

摘要翻译： 用于图形辅助有缺陷的MCM TF布线网的部分修复的过程。 该方法包括以下步骤：将薄膜器件的布线层插入测试器中，用测试仪扫描薄膜器件的布线层，识别布线网中的缺陷，根据每个 的缺陷接线网，并根据优先级修复缺陷。

公开(公告)号：US5895230A

公开(公告)日：1999-04-20

申请号：US949097

申请日：1997-10-10

申请人： Gerald K. Bartley

发明人： Gerald K. Bartley

IPC分类号： H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H01L21/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/5382 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/3011 ,  H01L2924/3025

摘要： An integrated circuit chip package having an electrical contact configurable for either signal or power/ground and a method for constructing the integrated circuit chip package are disclosed. The integrated circuit chip package includes a substrate for supporting an integrated circuit chip and a dedicated conductor for supplying voltage to the integrated circuit chip. A configurable contact is attached to a surface of the substrate. The integrated circuit chip package further includes a signal connection for electrically connecting a signal connector of an integrated circuit chip and the configurable contact. A removable connector electrically connects the configurable contact and the dedicated conductor, thereby enabling the configurable contact to be configured as either a signal or power/ground contact depending upon the absence or presence of the electrical connection between the configurable contact and the dedicated conductor provided by the removable connector.

摘要翻译： 公开了一种具有可配置用于信号或电源/接地的电接触的集成电路芯片封装以及用于构建集成电路芯片封装的方法。 集成电路芯片封装包括用于支撑集成电路芯片的基板和用于向集成电路芯片提供电压的专用导体。 可配置触点附着到基板的表面。 集成电路芯片封装还包括用于电连接集成电路芯片的信号连接器和可配置触点的信号连接。 可移动连接器将可配置触点和专用导体电连接，从而使可配置触点被配置为信号或电源/接地触点，这取决于可配置触点和专用导体之间的电连接的不存在或存在， 可移动连接器。