公开(公告)号：US20140070393A1

公开(公告)日：2014-03-13

申请号：US13613564

申请日：2012-09-13

Applicant: Gerald K. Bartley ,  Charles L. Johnson ,  John E. Kelly, III ,  Joseph Kuczynski ,  David R. Motschman ,  Arvind K. Sinha ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

Inventor： Gerald K. Bartley ,  Charles L. Johnson ,  John E. Kelly, III ,  Joseph Kuczynski ,  David R. Motschman ,  Arvind K. Sinha ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

IPC: H01L23/367 ,  H01L21/02 ,  H01L23/00

CPC classification number: H01L23/367 ,  H01L21/02656 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/4275 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/95 ,  H01L25/0657 ,  H01L2224/10165 ,  H01L2224/13014 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83909 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad placed between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip and nanofibers aligned perpendicular to mating surfaces of the first chip and the second chip

Abstract translation: 具有增强的冷却装置的半导体芯片的芯片堆叠包括具有第一侧上的电路的第一芯片和通过连接器格栅电和机械地耦合到第一芯片的第二芯片。 该装置还包括放置在第一芯片和第二芯片之间的热界面材料垫，其中热界面材料垫包括平行于第一芯片和第二芯片的配合表面排列的纳米纤维，并且纳米纤维垂直于第一芯片和第二芯片的配合表面对齐 芯片和第二芯片

公开(公告)号：US20120052417A1

公开(公告)日：2012-03-01

申请号：US12870041

申请日：2010-08-27

Applicant: Matthew S. Doyle ,  Joseph Kuczynski ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

Inventor： Matthew S. Doyle ,  Joseph Kuczynski ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

IPC: G03F1/00 ,  G03F7/20 ,  C25D7/00 ,  G06F17/50

CPC classification number: G03F7/0035 ,  C25D5/022 ,  G03F7/2002 ,  H05K3/18 ,  H05K2201/098 ,  H05K2203/056 ,  H05K2203/0588 ,  H05K2203/1476

Abstract: In various embodiments of the present invention a circuit apparatus having a rounded trace, a method to manufacture the circuit apparatus, and a design structure used in the design, testing, or manufacturing of the circuit apparatus are described. An artwork layer having an adaptable-mask section allows a graded amount of light to pass into an underlying photoresist layer. Subsequent to developing the photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least a portion of a rounded trace. The photoresist layer is removed resulting in a circuit apparatus having a rounded trace.

Abstract translation: 在本发明的各种实施例中，描述了具有圆形轨迹的电路设备，制造电路设备的方法以及在电路设备的设计，测试或制造中使用的设计结构。 具有适应性掩模部分的艺术品层允许渐变量的光通过下面的光致抗蚀剂层。 在显影光致抗蚀剂层之后，渐变量的光产生用作模具或侧壁的圆形几何空隙，用于产生至少一部分圆形迹线。 去除光致抗蚀剂层，得到具有圆形迹线的电路装置。

公开(公告)号：US20100243716A1

公开(公告)日：2010-09-30

申请号：US12410726

申请日：2009-03-25

Applicant: Joseph Kuczynski ,  Arvind K. Sinha ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

Inventor： Joseph Kuczynski ,  Arvind K. Sinha ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

IPC: B23K31/02 ,  B23K37/04 ,  H01R43/02 ,  H05K7/20

CPC classification number: H01R43/0256 ,  B23K1/0016 ,  B23K2101/36 ,  Y10T29/49213

Abstract: A method, system and apparatus for preferential cooling of an electrical circuit board via a cradle having a cooling shell. An enhanced connector cradle enables the secure and precise placement of a connector on a circuit board by using a cooling component which selectively enables only the connector leads to reach reflow temperature levels. The cradle aligns and securely connects the circuit board to the connector via a comb structure of the cradle to form a single connector unit. Heat is applied to the single connector unit to initiate bond formation. The cradle selectively minimizes the heat to the circuit board and other board components by enabling the circulation of de-ionized water through the cooling component during the heating process. As a result, the cradle restricts reflow temperature levels to the connector leads. The cradle mechanism is removed from the board after the connector is securely bonded to the board.

Abstract translation: 一种用于经由具有冷却壳的支架优先冷却电路板的方法，系统和装置。 增强的连接器支架通过使用选择性地使得连接器引线达到回流温度水平的冷却部件能够将连接器安全且精确地放置在电路板上。 支架通过支架的梳状结构将电路板对准并牢固地连接到连接器，以形成单个连接器单元。 将热量施加到单个连接器单元以引发结合形成。 支架通过在加热过程中通过冷却部件的循环使选择性地最小化对电路板和其它板部件的热量。 因此，支架限制了连接器引线的回流温度水平。 将连接器牢固地连接到电路板之后，将托架机构从电路板上取下。

公开(公告)号：US08434222B2

公开(公告)日：2013-05-07

申请号：US12870072

申请日：2010-08-27

Applicant: Matthew S. Doyle ,  Joseph Kuczynski ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

Inventor： Matthew S. Doyle ,  Joseph Kuczynski ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

IPC: H05K3/02 ,  H05K3/10

CPC classification number: H05K1/0296 ,  C25D5/022 ,  C25D5/10 ,  C25D7/00 ,  H05K1/0245 ,  H05K3/18 ,  H05K3/184 ,  H05K2201/09672 ,  H05K2201/098 ,  H05K2203/056 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49155

Abstract: A first artwork layer having a first adaptable-mask section allows a graded amount of light to pass into an underlying first photoresist layer. Subsequent to developing the first photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least a lower portion of a rounded trace. A dielectric layer is laminated upon the lower portion and a second artwork layer having an second adaptable-mask section allows a graded amount of light to pass into a second photoresist layer. Subsequent to developing the second photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least an upper portion of a rounded trace. The photoresist and dielectric layers are removed resulting in a circuit apparatus having a rounded differential pair trace.

Abstract translation: 具有第一适应性掩模部分的第一艺术品层允许渐变量的光进入下面的第一光致抗蚀剂层。 在显影第一光致抗蚀剂层之后，分级的光产生用作模具或侧壁的圆形几何空隙，用于产生圆形迹线的至少下部。 电介质层层叠在下部，具有第二可适应掩模部分的第二艺术品层允许渐变量的光通过第二光致抗蚀剂层。 在显影第二光致抗蚀剂层之后，分级的光产生用作模具或侧壁的圆形几何空隙，用于至少形成圆形迹线的上部。 去除光致抗蚀剂和介电层，导致具有圆形差分对迹线的电路设备。

公开(公告)号：US20130020716A1

公开(公告)日：2013-01-24

申请号：US13188572

申请日：2011-07-22

Applicant: Joseph KUCZYNSKI ,  Arvind K. SINHA ,  Kevin A. SPLITTSTOESSER ,  Timothy J. TOFIL

Inventor： Joseph KUCZYNSKI ,  Arvind K. SINHA ,  Kevin A. SPLITTSTOESSER ,  Timothy J. TOFIL

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L23/36 ,  H01L23/373 ,  H01L23/42 ,  H01L23/4275 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/131 ,  H01L2224/14131 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/29099 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad placed between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip. The method includes creating a first chip with circuitry on a first side and creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The method further includes placing a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip.

Abstract translation: 具有增强的冷却装置的半导体芯片的芯片堆叠包括具有第一侧上的电路的第一芯片和通过连接器格栅电和机械地耦合到第一芯片的第二芯片。 该装置还包括放置在第一芯片和第二芯片之间的热界面材料垫，其中热界面材料垫包括平行于第一芯片和第二芯片的配合表面排列的纳米纤维。 该方法包括在第一侧上创建具有电路的第一芯片，并通过连接器网格将第二芯片电连接并机械耦合到第一芯片。 该方法还包括在第一芯片和第二芯片之间放置热界面材料垫，其中热界面材料垫包括平行于第一芯片和第二芯片的配合表面排列的纳米纤维。

公开(公告)号：US20120048600A1

公开(公告)日：2012-03-01

申请号：US12870072

申请日：2010-08-27

Applicant: Matthew S. Doyle ,  Joseph Kuczynski ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

Inventor： Matthew S. Doyle ,  Joseph Kuczynski ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

IPC: H05K1/03 ,  C25D7/00 ,  G03F7/20 ,  G06F17/50 ,  B05D5/12

CPC classification number: H05K1/0296 ,  C25D5/022 ,  C25D5/10 ,  C25D7/00 ,  H05K1/0245 ,  H05K3/18 ,  H05K3/184 ,  H05K2201/09672 ,  H05K2201/098 ,  H05K2203/056 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49155

Abstract: A first artwork layer having a first adaptable-mask section allows a graded amount of light to pass into an underlying first photoresist layer. Subsequent to developing the first photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least a lower portion of a rounded trace. A dielectric layer is laminated upon the lower portion and a second artwork layer having an second adaptable-mask section allows a graded amount of light to pass into a second photoresist layer. Subsequent to developing the second photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least an upper portion of a rounded trace. The photoresist and dielectric layers are removed resulting in a circuit apparatus having a rounded differential pair trace.

Abstract translation: 具有第一适应性掩模部分的第一艺术品层允许渐变量的光进入下面的第一光致抗蚀剂层。 在显影第一光致抗蚀剂层之后，分级的光产生用作模具或侧壁的圆形几何空隙，用于产生圆形迹线的至少下部。 电介质层层叠在下部，具有第二可适应掩模部分的第二艺术品层允许渐变量的光通过第二光致抗蚀剂层。 在显影第二光致抗蚀剂层之后，分级的光产生用作模具或侧壁的圆形几何空隙，用于至少形成圆形迹线的上部。 去除光致抗蚀剂和介电层，导致具有圆形差分对迹线的电路设备。

公开(公告)号：US20120018666A1

公开(公告)日：2012-01-26

申请号：US12842200

申请日：2010-07-23

Applicant: Joseph Kuczynski ,  Arvind K. Sinha ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

Inventor： Joseph Kuczynski ,  Arvind K. Sinha ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

IPC: B29C39/42 ,  C09K5/14

CPC classification number: B82Y40/00 ,  B82Y30/00 ,  C01B32/15 ,  C01B32/20 ,  H01L23/373 ,  H01L23/3733 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The exemplary embodiments of the present invention provide a method and system for aligning graphite nanofibers in a thermal interface material to enhance the thermal interface material performance. The method includes preparing the graphite nanofibers in a herringbone configuration, and dispersing the graphite nanofibers in the herringbone configuration into the thermal interface material. The method further includes applying a magnetic field of sufficient intensity to align the graphite nanofibers in the thermal interface material. The system includes the graphite nanofibers configured in a herringbone configuration and a means for dispersing the graphite nanofibers in the herringbone configuration into the thermal interface material. The system further includes a means for applying a magnetic field of sufficient intensity to align the graphite nanofibers in the thermal interface material.

Abstract translation: 本发明的示例性实施例提供了一种用于在石墨纳米纤维中对准热界面材料以提高热界面材料性能的方法和系统。 该方法包括以人字形配置制备石墨纳米纤维，并将石英纳米纤维以人字形构型分散到热界面材料中。 该方法还包括施加足够强度的磁场以使石墨纳米纤维在热界面材料中对准。 该系统包括以人字形配置的石墨纳米纤维和用于将人字形配置中的石墨纳米纤维分散到热界面材料中的装置。 该系统还包括用于施加足够强度的磁场以对准热界面材料中的石墨纳米纤维的装置。

公开(公告)号：US09257359B2

公开(公告)日：2016-02-09

申请号：US13188572

申请日：2011-07-22

Applicant: Joseph Kuczynski ,  Arvind K. Sinha ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

Inventor： Joseph Kuczynski ,  Arvind K. Sinha ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

IPC: H01L23/48 ,  H01L21/50 ,  H01L23/36 ,  H01L23/373 ,  H01L23/42 ,  H01L23/427 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/36 ,  H01L23/373 ,  H01L23/42 ,  H01L23/4275 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/131 ,  H01L2224/14131 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/29099 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad placed between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip. The method includes creating a first chip with circuitry on a first side and creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The method further includes placing a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip.

Abstract translation: 具有增强的冷却装置的半导体芯片的芯片堆叠包括具有第一侧上的电路的第一芯片和通过连接器格栅电和机械地耦合到第一芯片的第二芯片。 该装置还包括放置在第一芯片和第二芯片之间的热界面材料垫，其中热界面材料垫包括平行于第一芯片和第二芯片的配合表面排列的纳米纤维。 该方法包括在第一侧上创建具有电路的第一芯片，并通过连接器网格将第二芯片电连接并机械耦合到第一芯片。 该方法还包括在第一芯片和第二芯片之间放置热界面材料垫，其中热界面材料垫包括平行于第一芯片和第二芯片的配合表面排列的纳米纤维。

公开(公告)号：US20120217987A1

公开(公告)日：2012-08-30

申请号：US13033801

申请日：2011-02-24

Applicant: Joseph Kuczynski ,  Wayne J. Rothschild ,  Kevin A. Splittstoesser

Inventor： Joseph Kuczynski ,  Wayne J. Rothschild ,  Kevin A. Splittstoesser

IPC: G01R27/26 ,  G01R31/00 ,  H05K1/00

CPC classification number: G01N27/223 ,  G01N27/221 ,  G01N27/225 ,  G01N27/226 ,  G01N33/246 ,  G01R1/04 ,  G01R1/0408 ,  G01R27/26 ,  G01R31/00 ,  G01R31/2817 ,  G01R31/2818 ,  G01R31/2851 ,  G01R31/2886 ,  G01R31/2887 ,  H05K1/00 ,  H05K1/0268 ,  H05K1/162 ,  H05K2203/162

Abstract: Two test coupons are utilized in an apparatus, method and design process/structure for determining the moisture content in an electronic circuit board (e.g., a printed circuit board (PCB) or panel). The first coupon has a laminate stack-up with voltage planes separated from each other by dielectric material. These voltage planes include etched clearances with neither plated through holes (PTHs) nor drilled holes extending therethrough. The second coupon is substantially identical to the first coupon except that each of the voltage planes of the first coupon includes PTHs extending through etched clearances corresponding to the etched clearances of the first coupon. In one embodiment, an alarm indicating unacceptably high moisture content is generated if a delta capacitance calculated as a difference between capacitance measurements acquired from the respective coupons is greater than a threshold. Preferably, the alarm notifies a user that at least one aqueous process related to PTH formation is implicated.

Abstract translation: 在用于确定电子电路板（例如，印刷电路板（PCB）或面板）中的水分含量的装置，方法和设计过程/结构中使用两个测试试样。 第一个优惠券具有层压叠层，电压平面通过电介质材料彼此分开。 这些电压平面包括没有电镀通孔（PTH）的蚀刻间隙和贯穿其中的钻孔。 除了第一试样的每个电压平面包括延伸通过对应于第一试样的蚀刻间隙的蚀刻间隙的PTH之外，第二试样基本上与第一试样基本相同。 在一个实施例中，如果根据从各个优惠券获取的电容测量值之差计算的增量电容大于阈值，则产生指示不可接受的高水分含量的警报。 优选地，警报通知用户涉及与PTH形成有关的至少一个含水过程。

公开(公告)号：US09229318B2

公开(公告)日：2016-01-05

申请号：US12870041

申请日：2010-08-27

Applicant: Matthew S. Doyle ,  Joseph Kuczynski ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

Inventor： Matthew S. Doyle ,  Joseph Kuczynski ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

IPC: G03F7/20 ,  G03F7/00 ,  C25D5/02 ,  H05K3/18

CPC classification number: G03F7/0035 ,  C25D5/022 ,  G03F7/2002 ,  H05K3/18 ,  H05K2201/098 ,  H05K2203/056 ,  H05K2203/0588 ,  H05K2203/1476

Abstract: In various embodiments of the present invention a circuit apparatus having a rounded trace, a method to manufacture the circuit apparatus, and a design structure used in the design, testing, or manufacturing of the circuit apparatus are described. An artwork layer having an adaptable-mask section allows a graded amount of light to pass into an underlying photoresist layer. Subsequent to developing the photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least a portion of a rounded trace. The photoresist layer is removed resulting in a circuit apparatus having a rounded trace.

Abstract translation: 在本发明的各种实施例中，描述了具有圆形轨迹的电路设备，制造电路设备的方法以及在电路设备的设计，测试或制造中使用的设计结构。 具有适应性掩模部分的艺术品层允许渐变量的光通过下面的光致抗蚀剂层。 在显影光致抗蚀剂层之后，渐变量的光产生用作模具或侧壁的圆形几何空隙，用于产生至少一部分圆形迹线。 去除光致抗蚀剂层，得到具有圆形迹线的电路装置。