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235 条记录 (耗时 0.033 秒)

    Benzenesulfonamide derivatives and use thereof
    71.
    发明授权
    Benzenesulfonamide derivatives and use thereof 失效
    苯磺酰胺衍生物及其用途

    公开(公告)号：US5597848A

    公开(公告)日：1997-01-28

    申请号：US397068

    申请日：1995-03-16

    申请人： Yasuo Ito ,  Hideo Kato ,  Shingo Yasuda ,  Nobuo Ogawa ,  Shunichiro Sakurai ,  Tomio Suzuki

    发明人： Yasuo Ito ,  Hideo Kato ,  Shingo Yasuda ,  Nobuo Ogawa ,  Shunichiro Sakurai ,  Tomio Suzuki

    IPC分类号： C07C311/19 ,  C07C311/29 ,  A61K31/24

    CPC分类号： C07C311/29 ,  C07C311/19

    摘要： A benzenesulfonamide derivative represented by the following general formula: ##STR1## wherein R.sup.1 represents a hydrogen atom, a lower alkyl group, a lower alkoxy group or a halogen atom; R.sup.2 represents a C.sub.1 -C.sub.10 straight- or branched-chain alkyl group, a C.sub.3 -C.sub.8 cycloalkyl group which may be substituted with one or more C.sub.1 -C.sub.6 alkyl groups on its ring, a C.sub.1 -C.sub.6 alkyl group substituted with one or more C.sub.3 -C.sub.8 cycloalkyl groups, 1-adamantylmethyl group, 2-norbornylmethyl group, or a C.sub.1 -C.sub.6 alkyl group substituted with one or more phenyl groups whose benzene ring may have one or more substituents; R.sup.3 represents a hydrogen atom or a lower alkyl group; and n is an integer of from 2 to 4, and a pharmacologically acceptable salt thereof. The present compounds have thromboxane A.sub.2 antagonistic activity, leucotriene antagonistic activity and the like and useful as a platelet aggregation inhibitor, antithrombotic agent, antiasthmatic agent and antiallergic agent.

    摘要翻译： PCT No.PCT / JP93 / 01382 Sec。 371日期1995年3月16日 102（e）1995年3月16日PCT PCT 1993年9月29日PCT公布。 公开号WO94 / 07848 日本1994年4月14日由以下通式表示的苯磺酰胺衍生物：其中R 1表示氢原子，低级烷基，低级烷氧基或卤素原子; R2表示C1-C10直链或支链烷基，可以在其环上被一个或多个C 1 -C 6烷基取代的C 3 -C 8环烷基，被一个或多个C 3取代的C 1 -C 6烷基 -C8环烷基，1-金刚烷基甲基，2-降冰片基甲基或被苯环可以具有一个或多个取代基的一个或多个苯基取代的C 1 -C 6烷基; R3表示氢原子或低级烷基; n为2〜4的整数，及其药理学上可接受的盐。 本发明化合物具有血栓素A2拮抗活性，白三烯拮抗活性等，可用作血小板聚集抑制剂，抗血栓形成剂，止喘剂和抗过敏剂。

    Non-volatile semiconductor memory device
    72.
    发明授权
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US5576994A

    公开(公告)日：1996-11-19

    申请号：US428060

    申请日：1995-04-25

    申请人： Hideo Kato ,  Nobutake Sugiura ,  Kiyotaka Uchigane ,  Masamichi Asano

    发明人： Hideo Kato ,  Nobutake Sugiura ,  Kiyotaka Uchigane ,  Masamichi Asano

    IPC分类号： G11C8/08 ,  G11C16/16 ,  G11C16/28 ,  G11C16/34 ,  G11C29/50 ,  G11C7/00

    CPC分类号： G11C16/345 ,  G11C16/16 ,  G11C16/28 ,  G11C16/344 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C8/08 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/5004

    摘要： When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly. Further, the erasure is effected until the threshold level of a memory cell of the highest erasure speed reaches a predetermined level, irrespective of the threshold distribution width of the memory cells, thus realizing a higher speed access to the device of narrower threshold distribution width, as compared with the conventional device.

    摘要翻译： 当擦除电压施加到每个具有浮动栅极的数据可擦除和可重写存储单元的源时，可以通过控制擦除电压的上升时间或逐步增加擦除电压来提高存储器单元的擦除特性。 在测试模式下，行解码器不选择行行，并且进一步将各存储单元的源设置为地电平。 在这些条件下，在存在过度存储单元的情况下，该单元由于耗尽而导通，从而可以基于连接到该存储单元的列线的电位变化来检测过度存储存储单元的存在 打开内存单元。 差分放大器用于检测列线的电位变化。 在测试模式中，将列线的电位与施加到虚拟列线的参考电位进行比较，并且源偏置产生电路将适合于测试的测试电位施加到单元的各个源，以将阈值电平 例如，各个单元的正方向。 通过将该测试电位施加到单元，可以检测正向偏移的伪阈值电平; 也就是说，更正确地检测存储器单元的过渡状态。 此外，擦除是直到最高擦除速度的存储单元的阈值水平达到预定水平，而不管存储器单元的阈值分布宽度如何，从而实现对较窄阈值分布宽度的设备的更高速度访问， 与常规装置相比。

    Semiconductor integrated circuit
    73.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US5548559A

    公开(公告)日：1996-08-20

    申请号：US448852

    申请日：1995-05-24

    申请人： Yoshio Mochizuki ,  Hideo Kato ,  Nobutake Sugiura

    发明人： Yoshio Mochizuki ,  Hideo Kato ,  Nobutake Sugiura

    IPC分类号： G06F12/06 ,  G11C8/12 ,  G11C16/20 ,  G11C17/00 ,  G11C8/00

    CPC分类号： G11C16/20 ,  G11C8/12

    摘要： A semiconductor integrated circuit includes a chip address data designation circuit, which has nonvolatile circuit characteristics or nonvolatilely programmed wiring corresponding to a chip address assigned to each of semiconductor chips connected to common buses, to output first chip address data corresponding to the chip address upon receiving an operation power supply voltage. The semiconductor integrated circuit further includes a chip address data latch circuit for latching second chip address data supplied from outside to the semiconductor chip, and a chip selection control circuit for comparing the first chip address data and the second chip address data, and generating a chip selection signal for activating the semiconductor chip when the first chip address data and the second chip address data coincide with each other. The chip address assigned to each semiconductor chip can be stored nonvolatilely, and one of the chips can be selected in response to the chip address supplied from outside the chip.

    摘要翻译： 半导体集成电路包括芯片地址数据指定电路，其具有对应于分配给连接到公共总线的每个半导体芯片的芯片地址的非易失性电路特性或非易失性编程布线，以在接收时输出与芯片地址对应的第一芯片地址数据 操作电源电压。 半导体集成电路还包括用于锁存从外部向半导体芯片提供的第二芯片地址数据的芯片地址数据锁存电路，以及用于比较第一芯片地址数据和第二芯片地址数据的芯片选择控制电路，以及产生芯片 当第一芯片地址数据和第二芯片地址数据彼此一致时激活半导体芯片的选择信号。 分配给每个半导体芯片的芯片地址可以被非易失性地存储，并且可以响应于从芯片外部提供的芯片地址来选择一个芯片。

    5-amino-8-methyl-7-pyrrolidinylquinoline-3-carboxylic acid derivative
    74.
    发明授权
    5-amino-8-methyl-7-pyrrolidinylquinoline-3-carboxylic acid derivative 失效
    5-氨基-8-甲基-7-吡咯烷基喹啉-3-羧酸衍生物

    公开(公告)号：US5547962A

    公开(公告)日：1996-08-20

    申请号：US261446

    申请日：1994-06-17

    申请人： Yasuo Ito ,  Hideo Kato ,  Singo Yasuda ,  Noriyuki Kado ,  Toshihiko Yoshida ,  Yoichi Yamamoto

    发明人： Yasuo Ito ,  Hideo Kato ,  Singo Yasuda ,  Noriyuki Kado ,  Toshihiko Yoshida ,  Yoichi Yamamoto

    IPC分类号： C07D401/04 ,  A61K31/47 ,  A61K31/4725 ,  A61P31/04 ,  C07D215/56 ,  C07D215/233

    CPC分类号： C07D215/56 ,  C07D401/04

    摘要： A 5-amino-8-methyl-7-pyrrolidinylquinoline-3-carboxylic acid derivative represented by the general formula: ##STR1## wherein R.sup.1 is a hydrogen atom or a lower alkyl group; R.sup.2 is a hydrogen atom, a lower alkyl group, a lower alkanoyl group, a halogenated lower alkanoyl group or a residue of carboxylic acid ester; R.sup.3 is a hydrogen atom or a lower alkyl group; R.sup.4, R.sup.5 or R.sup.6 are each independently a hydrogen atom or a lower alkyl group; or two of R.sup.4, R.sup.5 and R.sup.6 may be taken together to form a --(CH.sub.2).sub.n -group wherein n is 1 or 2, a stereoisomer thereof, or a pharmacologically acceptable salt thereof, the process for preparing these compounds, a pharmaceutical composition comprising an effective amount of these compounds and methods for the treatment of infectious diseases through the administration to patients of an effective amount of these compounds, and intermediates of these compounds are disclosed. These compounds are effective as antibacterial agents.

    摘要翻译： 由以下通式表示的5-氨基-8-甲基-7-吡咯烷基喹啉-3-羧酸衍生物：其中R1是氢原子或低级烷基; R2是氢原子，低级烷基，低级烷酰基，卤代低级烷酰基或羧酸酯的残基; R3是氢原子或低级烷基; R4，R5或R6各自独立地为氢原子或低级烷基; 或R 2，R 5和R 6中的两个可以一起形成其中n为1或2的 - （CH 2）n - 基团，其立体异构体或其药理学上可接受的盐，制备这些化合物的方法，药物组合物 包括有效量的这些化合物和通过向患者施用有效量的这些化合物来治疗感染性疾病的方法，以及这些化合物的中间体。 这些化合物作为抗菌剂是有效的。

    Apparatus and method for reading multi-level data stored in a semiconductor memory
    76.
    发明授权
    Apparatus and method for reading multi-level data stored in a semiconductor memory 失效
    用于读取存储在半导体存储器中的多电平数据的装置和方法

    公开(公告)号：US5457650A

    公开(公告)日：1995-10-10

    申请号：US272682

    申请日：1994-07-08

    申请人： Nobutake Sugiura ,  Hideo Kato ,  Yoshio Mochizuki

    发明人： Nobutake Sugiura ,  Hideo Kato ,  Yoshio Mochizuki

    IPC分类号： G11C11/56 ,  G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  H01L21/8246 ,  H01L27/112 ,  G11C11/34

    CPC分类号： G11C11/5692 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/32 ,  G11C2211/5642 ,  G11C8/14

    摘要： A semiconductor memory includes memory cells, word lines, bit lines, a row decoder, column decoder, a voltage-changing circuit, a sense amplifier, and an output circuit. Each memory cell stores multi-level data. The row decoder selects one of the word lines in accordance with an address signal. The voltage-changing circuit generates different voltages, which are applied to the row decoder. The different voltages are sequentially applied from the voltage-changing circuit to the word line selected by the row decoder. The column decoder selects a bit line every time the potential of the word line changes. The sense amplifier detects the data read from the memory cell onto the bit line every time the potential of the word line changes. The output circuit converts the data to code data.

    摘要翻译： 半导体存储器包括存储单元，字线，位线，行解码器，列解码器，电压改变电路，读出放大器和输出电路。 每个存储单元存储多级数据。 行解码器根据地址信号选择一个字线。 电压变化电路产生施加到行解码器的不同电压。 从电压变化电路依次施加不同的电压到由行解码器选择的字线。 每当字线的电位变化时，列解码器选择位线。 每次字线的电位改变时，读出放大器检测从存储单元读取到位线上的数据。 输出电路将数据转换为代码数据。

    Measuring system using a robot
    80.
    发明授权
    Measuring system using a robot 失效
    使用机器人的测量系统

    公开(公告)号：US5156053A

    公开(公告)日：1992-10-20

    申请号：US656060

    申请日：1991-02-19

    申请人： Mitsuru Shiraishi ,  Hideo Kato

    发明人： Mitsuru Shiraishi ,  Hideo Kato

    IPC分类号： G01N3/02 ,  G01N3/06 ,  G01N3/08 ,  G01N3/20

    CPC分类号： G01N3/20 ,  G01N3/08 ,  G01N2203/0218 ,  G01N2203/0682

    摘要： A robot measuring system automatically measures a mechanical characteristics of an object to be measured. The system includes a pressing robot for adding a predetermined pressing force to the object to be measured. An inner force sensor is mounted to one end of the pressing robot and detects strength of the pressing force through a pressing rod. A displacement gauge touches the object and detects a mechanical distortion caused in the object by the pressing force, a sensing robot supports the displacement gauge and moves the displacement gauge to a measuring position. A microprocessor inputs a detection result of the inner force sensor, controls a motion of the pressing robot based on the detection result, and calculates various mechanical characteristics based on a detection result input from the displacement gauge. A memory stores the various mechanical characteristics calculated from the microprocessor. Calculation of the mechanical characteristics of the plastic article is performed by the microprocessor by using a spline smoothing method.

    摘要翻译： PCT No.PCT / JP90 / 00800 Sec。 371日期1991年2月19日 102（e）1991年2月19日PCT申请1990年6月19日PCT公布。 公开号WO90 / 15982 日期1990年12月27日。机器人测量系统自动测量待测物体的机械特性。 该系统包括用于向待测量对象添加预定按压力的按压机器人。 内力传感器安装在按压机器人的一端，并通过按压杆检测按压力的强度。 位移计接触物体，通过按压力检测物体中引起的机械变形，感测机器人支撑位移计并将位移计移动到测量位置。 微处理器输入内力传感器的检测结果，根据检测结果控制按压机器人的运动，并根据从位移计输入的检测结果计算各种机械特性。 存储器存储从微处理器计算的各种机械特性。 通过使用花键平滑法由微处理器执行塑料制品的机械特性的计算。