公开(公告)号：US20180004269A1

公开(公告)日：2018-01-04

申请号：US15197083

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Nir Rosenzweig ,  Efraim Rotem ,  Alexander Gendler ,  Ankush Varma

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/28 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3243 ,  G06F1/325 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/38 ,  G06F9/44 ,  Y02D10/126 ,  Y02D10/152

Abstract: A processor includes an execution engine and a power controller. The execution engine includes circuitry to determine an increased current for the execution engine. The power controller includes circuitry to determine a new dynamic capacitance for the execution engine based upon the increased current, calculate a new power consumption for the execution engine based upon the new dynamic capacitance, utilize the new power consumption to evaluate a new aggregate demand for power of a plurality of engines including the execution engine, and evaluate power provisioning of the processor based upon the new power consumption for the execution engine.

公开(公告)号：US09684595B2

公开(公告)日：2017-06-20

申请号：US15162707

申请日：2016-05-24

Applicant: Intel Corporation

Inventor： Larisa Novakovsky ,  Joseph Nuzman ,  Alexander Gendler

IPC: G06F12/0871 ,  G06F12/0897 ,  G06F12/0811 ,  G06F12/0891 ,  G06F12/0804 ,  G06F12/0837 ,  G06F12/0831

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0831 ,  G06F12/0837 ,  G06F12/0891 ,  G06F2212/283 ,  G06F2212/621

Abstract: A method for determining an inclusion policy includes determining a ratio of a capacity of a large cache to a capacity of a core cache in a cache subsystem of a processor and selecting an inclusive policy as the inclusion policy for the cache subsystem in response to the cache ratio exceeding an inclusion threshold. The method may further include selecting a non-inclusive policy in response to the cache ratio not exceeding the inclusion threshold and, responsive to a cache transaction resulting in a cache miss, performing an inclusion operation that invokes the inclusion policy.

公开(公告)号：US09660799B1

公开(公告)日：2017-05-23

申请号：US14950319

申请日：2015-11-24

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Ernest Knoll ,  Ofer Nathan ,  Michael Mishaeli ,  Krishnakanth V. Sistla ,  Ariel Sabba ,  Shani Rehana ,  Ariel Szapiro ,  Tsvika Kurts ,  Ofer Levy

IPC: G06F1/06 ,  H04L7/033 ,  H04L7/00

CPC classification number: H04L7/0331 ,  G06F1/08 ,  G06F1/10 ,  G06F1/324 ,  H04L7/0025 ,  H04L7/005 ,  Y02D10/126

Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.

公开(公告)号：US20170070242A1

公开(公告)日：2017-03-09

申请号：US15355199

申请日：2016-11-18

Applicant: INTEL CORPORATION

Inventor： Alexander Gendler ,  Gilad Cohen

IPC: H03M13/29 ,  H03M13/13 ,  H03M13/00 ,  G06F11/10

CPC classification number: H03M13/2906 ,  G06F11/1008 ,  H03M13/13 ,  H03M13/616

Abstract: Described is a processor with a data storage structure operative to store data and a first error correction code that corresponds to the data. The processor further includes circuitry to compare the first and second error correction codes to obtain a comparison result. There are no errors in the data when the comparison result is equal to zero and there is at least one error in the data when the comparison result is not equal to zero. The circuitry corrects a single bit error of the data when the comparison result matches one of the unique combination of bit values of one of the plurality of bit groups in the generator matrix and corrects two consecutive data bits of the data when the comparison result corresponds to a predefined number of values as a result of an exclusive-or (XOR) operation performed on two consecutive bit groups of the generator matrix.

Abstract translation: 描述了具有可操作地存储数据的数据存储结构和对应于数据的第一纠错码的处理器。 处理器还包括用于比较第一和第二纠错码以获得比较结果的电路。 当比较结果等于零时，数据中没有错误，并且当比较结果不等于零时，数据中至少有一个错误。 当比较结果与发生器矩阵中的多个位组之一的位值的唯一组合之一匹配时，电路校正数据的单个位错误，并且当比较结果对应于数据时校正数据的两个连续数据位 作为对发生器矩阵的两个连续位组执行异或（XOR）操作的结果的预定数量的值。

公开(公告)号：US20160378660A1

公开(公告)日：2016-12-29

申请号：US14751889

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Ariel Berkovits ,  Michael Mishaeli ,  Nadav Shulman ,  Sameer Desai ,  Shani Rehana ,  Ittai Anati ,  Hisham Shafi

IPC: G06F12/08 ,  G11C11/406 ,  G06F1/32 ,  G11C7/10

CPC classification number: G06F1/3287 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0888 ,  G06F12/1433 ,  G06F2212/1052 ,  G06F2212/311 ,  G06F2212/621

Abstract: A method and apparatus for flushing and restoring core memory content to and from, respectively, external memory are described. In one embodiment, the apparatus is an integrated circuit comprising a plurality of processor cores, the plurality of process cores including one core having a first memory operable to store data of the one core, the one core to store data from the first memory to a second memory located externally to the processor in response to receipt of a first indication that the one core is to transition from a first low power idle state to a second low power idle state and receipt of a second indication generated externally from the one core indicating that the one core is to store the data from the first memory to the second memory, locations in the second memory at which the data is stored being accessible by the one core and inaccessible by other processor cores in the IC; and a power management controller coupled to the plurality of cores and located outside the plurality of cores.

Abstract translation: 描述了分别将外部存储器和/或从外部存储器内核心存储器内容清理和恢复的方法和装置。 在一个实施例中，该装置是包括多个处理器核心的集成电路，所述多个处理核心包括一个核心，其具有可操作以存储一个核心数据的第一存储器，所述一个核心将数据从第一存储器存储到 响应于接收到一个核心将从第一低功率空闲状态转换到第二低功率空闲状态的第一指示，并且接收到从一个核心外部产生的第二指示，该第二存储器位于处理器的外部，指示该 一个核心是将数据从第一存储器存储到第二存储器，存储数据的第二存储器中的位置可由一个核心访问，并且IC中的其他处理器核心不可访问; 以及耦合到所述多个核心并位于所述多个核心外部的电力管理控制器。

公开(公告)号：US20140281239A1

公开(公告)日：2014-09-18

申请号：US13843315

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Larisa Novakovsky ,  Joseph Nuzman ,  Alexander Gendler

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0831 ,  G06F12/0837 ,  G06F12/0891 ,  G06F2212/283 ,  G06F2212/621

Abstract: A method for determining an inclusion policy includes determining a ratio of a capacity of a large cache to a capacity of a core cache in a cache subsystem of a processor and selecting an inclusive policy as the inclusion policy for the cache subsystem in response to the cache ratio exceeding an inclusion threshold. The method may further include selecting a non-inclusive policy in response to the cache ratio not exceeding the inclusion threshold and, responsive to a cache transaction resulting in a cache miss, performing an inclusion operation that invokes the inclusion policy.

Abstract translation: 用于确定包含策略的方法包括确定大型缓存的容量与处理器的高速缓存子系统中的核心高速缓存的容量的比率，并且选择包含策略作为响应于高速缓存的高速缓存子系统的包含策略 比例超过包含阈值。 该方法还可以包括响应于不超过包含阈值的高速缓存比率选择不包含策略，并且响应于导致高速缓存未命中的高速缓存事务，执行调用包含策略的包含操作。

公开(公告)号：US12099597B2

公开(公告)日：2024-09-24

申请号：US18384996

申请日：2023-10-30

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Sagi Meller ,  Gavri Berger ,  Igor Yanover

IPC: G06F21/00 ,  G06F1/32 ,  G06F9/38 ,  G06F21/54 ,  G06F21/56

CPC classification number: G06F21/54 ,  G06F1/32 ,  G06F9/3802 ,  G06F21/561 ,  G06F2221/034

Abstract: An apparatus and method for intelligent power virus protection in a processor. For example, one embodiment of a processor comprises: first circuitry including an instruction fetch circuit to fetch instructions, each instruction comprising an instruction type and an associated width comprising a number of bits associated with source and/or destination operand values associated with the instruction; detection circuitry to detect one or more instructions of a particular type and/or width; evaluation circuitry to evaluate an impact of power virus protection (PVP) circuitry when executing the one or more instructions based on the detected instruction types and/or widths; and control circuitry, based on the evaluation, to configure the PVP circuitry in accordance with the evaluation performed by the evaluation circuitry.

公开(公告)号：US11442529B2

公开(公告)日：2022-09-13

申请号：US16412606

申请日：2019-05-15

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Ameya Ambardekar ,  Ankush Varma ,  Nimrod Angel ,  Nir Rosenzweig ,  Arik Gihon ,  Alexander Gendler ,  Rachid E. Rayess ,  Tamir Salus

IPC: G06F1/00 ,  G06F1/3234 ,  G06F1/3296 ,  G06F9/38 ,  G06F11/34

Abstract: In one embodiment, an apparatus comprises: a plurality of intellectual property (IP) circuits, each of the plurality of IP circuits including a configuration register to store a dynamic current budget; and a power controller coupled to the plurality of IP circuits, the power controller including a dynamic current sharing control circuit to receive current throttling hint information regarding a workload to be executed on at least some of the plurality of IP circuits and generate the dynamic current budget for each of the plurality of IP circuits based at least in part thereon. Other embodiments are described and claimed.

公开(公告)号：US11409560B2

公开(公告)日：2022-08-09

申请号：US16367581

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Krishnamurthy Jambur Sathyanarayana ,  Robert Valentine ,  Alexander Gendler ,  Shmuel Zobel ,  Gavri Berger ,  Ian M. Steiner ,  Nikhil Gupta ,  Eyal Hadas ,  Edo Hachamo ,  Sumesh Subramanian

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/30 ,  G06F9/4401 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3296

Abstract: In one embodiment, a processor includes a current protection controller to: receive instruction width information and instruction type information associated with one or more instructions stored in an instruction queue prior to execution of the one or more instructions by an execution circuit; determine a power license level for the core based on the corresponding instruction width information and the instruction type information; generate a request for a license for the core corresponding to the power license level; and communicate the request to a power controller when the one or more instructions are non-speculative, and defer communication of the request when at least one of the one or more instructions is speculative. Other embodiments are described and claimed.

公开(公告)号：US11237615B2

公开(公告)日：2022-02-01

申请号：US16836686

申请日：2020-03-31

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Efraim Rotem ,  Nir Rosenzweig ,  Krishnakanth V. Sistla ,  Ashish V. Choubal ,  Ankush Varma

IPC: G06F1/00 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3237

Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.