中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

80 records (took 0.026 seconds)

    Balanced control of processor temperature
    71.
    发明授权
    Balanced control of processor temperature 有权

    公开(公告)号：US09791904B2

    公开(公告)日：2017-10-17

    申请号：US14461039

    申请日：2014-08-15

    Applicant: Intel Corporation

    Inventor： Nir Rosenzweig ,  Doron Rajwan ,  Dorit Shapira ,  Nadav Shulman ,  Tomer Ziv

    IPC: G06F1/00 ,  G06F1/32 ,  G06F1/20 ,  G01K13/00

    CPC classification number: G06F1/206 ,  G01K1/026 ,  G01K13/00 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324

    Abstract: In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed.

    Programmable power management agent
    72.
    发明授权
    Programmable power management agent 有权

    公开(公告)号：US09710054B2

    公开(公告)日：2017-07-18

    申请号：US14634777

    申请日：2015-02-28

    Applicant: Intel Corporation

    Inventor： Israel Diamand ,  Asaf Rubinstein ,  Arik Gihon ,  Tal Kuzi ,  Tomer Ziv ,  Nadav Shulman

    IPC: G06F1/32 ,  G06F1/26

    CPC classification number: G06F1/3296 ,  G06F1/26 ,  G06F1/3228 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

    Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.

    Power consumption monitoring device for a power source
    76.
    发明授权
    Power consumption monitoring device for a power source 有权
    电源功耗监控装置

    公开(公告)号：US09500714B2

    公开(公告)日：2016-11-22

    申请号：US14040346

    申请日：2013-09-27

    Applicant: Intel Corporation

    Inventor： Efraim Rotem ,  Nir Rosenzweig ,  Jeffrey A. Carlson ,  Philip R. Lehwalder ,  Nadav Shulman ,  Doron Rajwan

    IPC: G01R19/252 ,  G01R31/36 ,  G01R21/133 ,  G01R22/10

    CPC classification number: G01R31/3648 ,  G01R21/133 ,  G01R22/10 ,  G01R31/3624

    Abstract: Examples are disclosed for an integrated circuit (IC) device coupled to a battery-operated power supply unit, such as an IC in a mobile computing device or wireless phone, to accurately determine energy usage drawn from the power supply unit under rapidly dynamic circumstances. A current sense signal of a power line from the power supply unit is digitized. The digitized current sense is added to an accumulator at a rate that is approximately proportional to a voltage of the power line from the power supply unit. The accumulator is then outputted and scaled to units relevant to energy measurements. The energy measurement is used to estimate remaining battery life. Triggering the digitization of the current sense signal may be by use of a pulse generation circuit, or by use of an overflow indicator of an accumulator for a digitized voltage sense signal.

    Abstract translation: 公开了用于耦合到诸如移动计算设备或无线电话中的IC的电池供电单元的集成电路（IC）设备的实例，以在快速动态的情况下精确地确定从电源单元获取的能量使用。 来自电源单元的电力线的电流感测信号被数字化。 数字化电流检测以与来自电源单元的电力线的电压近似成比例的速率被添加到累加器。 然后将累加器输出并缩放到与能量测量相关的单位。 能量测量用于估计剩余电池寿命。 触发电流检测信号的数字化可以通过使用脉冲发生电路，或者通过使用累加器的溢出指示符来进行数字化的电压检测信号。

    System maximum current protection
    77.
    发明授权
    System maximum current protection 有权
    系统最大电流保护

    公开(公告)号：US09477243B2

    公开(公告)日：2016-10-25

    申请号：US14579794

    申请日：2014-12-22

    Applicant: Intel Corporation

    Inventor： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Nadav Shulman ,  Gal Leibovich ,  Tomer Ziv ,  Amit Gabai ,  Jorge P. Rodriguez ,  Jeffrey A. Carlson

    IPC: G06F1/32 ,  G05F1/10 ,  H03L7/08

    CPC classification number: G06F1/324 ,  G05F1/10 ,  G06F1/28 ,  G06F1/3206 ,  H03L7/08 ,  Y02D10/126

    Abstract: A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.

    Abstract translation: 一种用于提供主动电流保护的方法和装置。 在一个实施例中，该方法包括：在转换到集成电路（IC）的新状态之前，通过针对多个域中的每个域计算预期电流来计算IC中多个域的预期功率之和 在新状态的单个域频率上，将预期电流与其相关联的电压乘以用于新状态的多个域中的每一个; 将总和与功率限制进行比较; 并且如果所述和大于所述功率极限，则减少与所述多个域中的至少一个域相关联的各个域频率，以将所述IC的总瞬时功率维持在所述功率极限以下。

    Dynamically allocating a power budget over multiple domains of a processor
    79.
    发明授权
    Dynamically allocating a power budget over multiple domains of a processor 有权
    在处理器的多个域上动态分配功率预算

    公开(公告)号：US09081557B2

    公开(公告)日：2015-07-14

    申请号：US14143939

    申请日：2013-12-30

    Applicant: Intel Corporation

    Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Nadav Shulman

    IPC: G06F1/26 ,  G06F9/50 ,  G06F1/32

    CPC classification number: G06F1/26 ,  G06F1/3243 ,  G06F9/5094 ,  Y02D10/152

    Abstract: In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括一种用于当前时间间隔确定多域处理器的功率预算的方法，确定要分配给处理器的第一和第二域的功率预算的一部分，以及控制频率 基于所分配的部分的域。 这样的确定和分配可以在处理器的运行期间动态地执行。 描述和要求保护其他实施例。

    Controlling A Turbo Mode Frequency Of A Processor
    80.
    发明申请
    Controlling A Turbo Mode Frequency Of A Processor 审中-公开
    控制处理器的Turbo模式频率

    公开(公告)号：US20150095673A1

    公开(公告)日：2015-04-02

    申请号：US14565723

    申请日：2014-12-10

    Applicant: Intel Corporation

    Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Wiessmann ,  Ryan Wells ,  Nadav Shulman

    IPC: G06F1/32

    CPC classification number: G06F1/3206 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3885 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171

    Abstract: In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括具有功率控制器以控制处理器工作频率的多核处理器。 更具体地，功率控制器可以将处理器的最大工作频率限制在小于配置的最大工作频率，以便能够减少响应于电力状态事件而发生的频率转换的数量，从而避免在处理这些操作时所执行的操作的开销 转换 描述和要求保护其他实施例。

Patent Agency Ranking