公开(公告)号：US20150212877A1

公开(公告)日：2015-07-30

申请号：US14166360

申请日：2014-01-28

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Karl Hofmann ,  Michael Goessel

IPC: G06F11/10 ,  G11C29/02 ,  G11C16/06 ,  G11C11/16 ,  G11C13/00

CPC classification number: G06F11/1008 ,  G06F11/1012 ,  G11C7/1006 ,  G11C11/165 ,  G11C11/1675 ,  G11C13/0021 ,  G11C13/0069 ,  G11C16/06 ,  G11C29/025 ,  G11C2029/0411 ,  H03M13/00 ,  H03M13/13 ,  H03M13/152 ,  H03M13/19 ,  H03M13/353 ,  H03M13/611 ,  H03M13/618

Abstract: An apparatus includes a processing unit and a memory. The processing unit is configured to encode a plurality of bits to obtain a plurality of encoded bits, the processing unit is configured to determine an inversion decision. When the inversion decision indicates that the subset of the encoded bits shall not be inverted, the processing unit is configured to store, as a stored word, bits of the first codeword into the memory. When the inversion decision indicates that the subset of the encoded bits shall be inverted, the processing unit is configured to invert each encoded bit of a subset of the encoded bits to obtain a second codeword and to store the second codeword into the memory.

Abstract translation: 一种装置包括处理单元和存储器。 处理单元被配置为对多个比特进行编码以获得多个编码比特，所述处理单元被配置为确定反演决定。 当反转决定指示编码比特的子集不被反转时，处理单元被配置为将第一码字的比特存储到存储器中作为存储字。 当反转决定指示编码比特的子集应被反转时，处理单元被配置为反转编码比特的子集的每个编码比特以获得第二码字并将第二码字存储到存储器中。

公开(公告)号：US08935590B2

公开(公告)日：2015-01-13

申请号：US13664495

申请日：2012-10-31

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Michael Goessel

IPC: G11C29/00 ,  G06F11/10 ,  G11C7/10

CPC classification number: G06F11/10 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1072 ,  G06F11/1076 ,  G11C7/1006

Abstract: A circuitry is provided that includes a memory including a plurality of memory cells, wherein at least one of the plurality of memory cells of the memory is configured to take on one of at least three different states. The circuitry also includes a first subcircuit BT configured to generate a plurality of ternary output values based on a sequence of binary values, a second subcircuit LH configured to transform one or more ternary state values into binary auxiliary read values based on the one or more state values, and an encoder configured to generate one or more binary check bits, wherein the encoder is configured to store each of the generated one or more check bits in a different memory cell.

Abstract translation: 提供了一种电路，其包括包括多个存储器单元的存储器，其中存储器的多个存储器单元中的至少一个被配置为采取至少三种不同状态中的一种。 电路还包括第一子电路BT，其被配置为基于二进制值的序列产生多个三进制输出值，第二子电路LH被配置为基于一个或多个状态将一个或多个三态状态值转换为二进制辅助读取值 值和被配置为生成一个或多个二进制校验位的编码器，其中所述编码器被配置为将所生成的一个或多个校验位中的每一个存储在不同的存储器单元中。

公开(公告)号：US20140198583A1

公开(公告)日：2014-07-17

申请号：US13743409

申请日：2013-01-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Thomas Kern ,  Jens Rosenbusch ,  Ulrich Backhausen ,  Thomas Nirschl

IPC: G11C16/24 ,  G11C16/10 ,  G11C16/14

CPC classification number: G11C16/14 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

Abstract: Embodiments relate to system and methods including a plurality of nonvolatile memory elements wherein sets of least two nonvolatile memory elements each share one select element for selecting one of the nonvolatile memory elements of a particular one of the sets of nonvolatile memory elements for a read operation or a program operation.

Abstract translation: 实施例涉及包括多个非易失性存储器元件的系统和方法，其中至少两个非易失性存储器元件的集合共享一个选择元件，用于选择用于读取操作的非易失性存储器元件组中的特定一个的非易失性存储器元件之一， 一个程序操作。

公开(公告)号：US12273125B2

公开(公告)日：2025-04-08

申请号：US17944510

申请日：2022-09-14

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Thomas Rabenalt ,  Michael Goessel

IPC: H03M13/15 ,  H03M13/00

Abstract: An approach for correcting at least one byte error in a binary sequence is proposed, the binary sequence comprising a plurality of bytes and being a code word of an error code in the error-free case. The approach comprises the steps of: (i) determining at least one byte error position signal which specifies whether or not a byte of the binary sequence is erroneous, (ii) determining at least one byte error correction value, based on which an erroneous byte position identified by means of the byte error position signal is correctable, the at least one byte error correction value being determined by virtue of a first value and a second value being determined for each of at least two byte positions based on a coefficient of the locator polynomial, and (iii) correcting the at least one byte error based on the at least one byte error correction value.

公开(公告)号：US20230091457A1

公开(公告)日：2023-03-23

申请号：US17944510

申请日：2022-09-14

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Thomas Rabenalt ,  Michael Goessel

IPC: H03M13/15 ,  H03M13/00

Abstract: An approach for correcting at least one byte error in a binary sequence is proposed, the binary sequence comprising a plurality of bytes and being a code word of an error code in the error-free case. The approach comprises the steps of: (i) determining at least one byte error position signal which specifies whether or not a byte of the binary sequence is erroneous, (ii) determining at least one byte error correction value, based on which an erroneous byte position identified by means of the byte error position signal is correctable, the at least one byte error correction value being determined by virtue of a first value and a second value being determined for each of at least two byte positions based on a coefficient of the locator polynomial, and (iii) correcting the at least one byte error based on the at least one byte error correction value.

公开(公告)号：US11362684B2

公开(公告)日：2022-06-14

申请号：US17191924

申请日：2021-03-04

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Michael Goessel

IPC: H03M13/00 ,  H03M13/39 ,  H03M13/25

Abstract: A method for detecting a code word is proposed, wherein the code word is a code word of one of at least two codes, wherein n states are read from memory cells of a memory, respectively. The n states are determined in a time domain for each of the at least two codes, wherein additionally n states are read from further memory cells and at least one reference value is determined therefrom and wherein the at least one reference value is taken as a basis for determining which of the at least two codes is the correct code. A corresponding device is furthermore specified.

公开(公告)号：US20210216221A1

公开(公告)日：2021-07-15

申请号：US17144723

申请日：2021-01-08

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Michael Goessel

IPC: G06F3/06

Abstract: Method for determining a resultant data word when accessing memory cells of a memory, comprising the steps: (a) reading a set of memory cells, (b) wherein a first data word and a second data word are determined from the read set of memory cells, wherein each memory cell is assigned a component of the first data word and the corresponding component of the second data word, (c) wherein the first data word and the second data word for the respective memory cell assume a first value if a first comparison with a first reference value and a second comparison with a second reference value show that the two reference values are greater and assume a second value if the first comparison with the first reference value and the second comparison with the second reference value show that the two reference values are smaller, (d) wherein the first data word and the second data word for the respective memory cell assume at least one third value if the conditions according to feature (c) are not satisfied, and (e) determining the resultant data word on the basis of the first data word or on the basis of the second data word. A corresponding device is also proposed.

公开(公告)号：US10812109B2

公开(公告)日：2020-10-20

申请号：US16178901

申请日：2018-11-02

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Christian Badack ,  Michael Goessel

IPC: H03M13/15

Abstract: A circuit arrangement for determining in parallel of at least two byte error position signals for identifying at least one byte error in a binary sequence comprising a plurality of bytes, wherein the binary sequence in the error-free case is a code word of an error code, the circuit arrangement is configured such that each of the at least two byte error position signals is determinable using components of an error syndrome of the error code such that the components indicate whether or not a byte of the binary sequence that is associated with the byte error position signal is erroneous.

公开(公告)号：US10319460B2

公开(公告)日：2019-06-11

申请号：US13966679

申请日：2013-08-14

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Jens Rosenbusch ,  Ulrich Backhausen ,  Thomas Nirschl

IPC: G11C29/50 ,  G11C16/34 ,  G06F11/16 ,  G11B20/18 ,  G06F11/10 ,  G11C29/02 ,  G11C29/42 ,  G11C29/52 ,  G11C16/28

Abstract: A memory system having a flexible read reference is disclosed. The system includes a memory partition, a failcount component, and a controller. The memory partition includes a plurality of memory cells. The failcount component is configured to generate failcounts in response to read operations of the memory partition. The controller is configured to calibrate a reference value for the memory partition by utilizing the failcounts.

公开(公告)号：US20190132006A1

公开(公告)日：2019-05-02

申请号：US16178901

申请日：2018-11-02

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Christian Badack ,  Michael Goessel

IPC: H03M13/15

Abstract: A circuit arrangement for determining in parallel of at least two byte error position signals for identifying at least one byte error in a binary sequence comprising a plurality of bytes, wherein the binary sequence in the error-free case is a code word of an error code, the circuit arrangement is configured such that each of the at least two byte error position signals is determinable using components of an error syndrome of the error code such that the components indicate whether or not a byte of the binary sequence that is associated with the byte error position signal is erroneous.