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公开(公告)号：US20180175839A1
公开(公告)日：2018-06-21
申请号：US15382155
申请日：2016-12-16
Applicant: Intel Corporation
Inventor： Chenchu Punnarao Bandi , Amit Kumar Srivastava
CPC classification number: H03K5/14 , H03K2005/00286 , H03L7/0818 , H03L7/091
Abstract: Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes a data path to receive data information based on timing of a data capture clock signal, a clock path including a delay circuit to apply a time delay to an input clock signal and generate a delayed clock signal, a clock tree circuit to provide the data capture clock signal and a first feedback clock signal based on the delayed clock signal, a circuitry including latches to sample the input clock signal based on timing of the feedback clock signal and provide sampled information, and a controller to control the delay circuit based on the sampled information in order to cause the data capture clock signal to be out of phase with the input clock signal by one-fourth of a period of the input clock signal.
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公开(公告)号：US09996131B2
公开(公告)日：2018-06-12
申请号：US14925713
申请日：2015-10-28
Applicant: Intel Corporation
Inventor： Amit Kumar Srivastava
CPC classification number: G06F1/266 , G06F13/4282
Abstract: Apparatuses, systems and methods associated with electrical fast transient tolerant input/output (I/O) communication (e.g., universal serial bus (USB)) design are disclosed herein. In embodiments, an apparatus may include common mode extraction circuitry to extract a common mode voltage from a USB input signal for a USB device, compare the common mode voltage with a reference voltage range and determine, based on the comparison, that the common mode voltage is outside of the reference voltage range. In the embodiments, the apparatus may further include processing circuitry to adjust the common mode voltage to within the reference voltage range. Other embodiments may be described and/or claimed.
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公开(公告)号：US20180157286A1
公开(公告)日：2018-06-07
申请号：US15366001
申请日：2016-12-01
Applicant: Intel Corporation
Inventor： Duane G. Quiet , Amit Kumar Srivastava , Kenneth P. Foust
IPC: G06F1/08 , G06F13/362
CPC classification number: G06F1/08 , G06F13/362
Abstract: In one embodiment, an apparatus includes a clock control circuit to generate a clock signal for communication on an interconnect. The clock control circuit may be configured to receive an indication of a next device of a plurality of devices to be accessed and to dynamically update a control signal to cause the communication of the clock signal to be dynamically switched between a fixed clock frequency and a spread spectrum clock frequency based at least in part on the indication of communication to the next device. Other embodiments are described and claimed.
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公开(公告)号：US20170346617A1
公开(公告)日：2017-11-30
申请号：US15162884
申请日：2016-05-24
Applicant: Intel Corporation
Inventor： Chenchu Punnarao Bandi , Amit Kumar Srivastava
CPC classification number: G11C7/222 , G06F1/10 , H03L7/00 , H03L7/091 , H04L7/0008 , H04L7/005 , H04L7/0079 , H04L7/0087 , H04L7/0091 , H04L7/033 , H04L7/041 , H04L25/14
Abstract: In one embodiment, an apparatus includes a clock channel to receive and distribute a clock signal to a plurality of data channels. At least some of the data channels may include: a first sampler to sample data; a second sampler to sample the data; and a deskew calibration circuit to receive first sampled data from the first sampler and second sampled data from the second sampler and generate a local calibration signal for use in the corresponding data channel. The apparatus may further include a global deskew calibration circuit to receive the clock signal from the clock channel, receive the first sampled data and the second sampled data from the plurality of data channels, and generate a global calibration signal for provision to the plurality of data channels. Other embodiments are described and claimed.
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公开(公告)号：US20160378632A1
公开(公告)日：2016-12-29
申请号：US14752042
申请日：2015-06-26
Applicant: Intel Corporation
Inventor： Amit Kumar Srivastava
CPC classification number: G06F11/3051 , G06F9/4411 , G06F11/1417 , G06F11/1423 , G06F11/3041 , G06F13/4286
Abstract: Techniques for port selection are described herein. The techniques may include an apparatus a transceiver including a plurality of ports. The apparatus includes a selector to select a port from among the plurality of ports. The port is selected to receive a repair operation to repair a basic input output system.
Abstract translation: 本文描述了用于端口选择的技术。 这些技术可以包括一种包括多个端口的收发机的装置。 该装置包括从多个端口中选择端口的选择器。 选择该端口接收修复操作以修复基本输入输出系统。
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Patent Agency Ranking
76.发明授权Apparatus and method for adaptive common mode noise decomposition and tuning 有权用于自适应共模噪声分解和调谐的装置和方法公开(公告)号：US09455752B2
公开(公告)日：2016-09-27
申请号：US14483486
申请日：2014-09-11
Applicant: Intel Corporation
Inventor： Khang Choong Yong , Boon Ping Koh , Amit Kumar Srivastava , Wil Choon Song
CPC classification number: H04B1/0475 , H03F1/34 , H03F3/24 , H04B1/0483 , H04B3/30 , H04B15/02 , H04B2001/0408 , H04B2001/0433 , H04B2215/00
Abstract: Described is an apparatus which comprises: a pre-driver coupled to a transmitter, the transmitter having a differential output; and a tuning circuit operable to couple to the differential output to tune the pre-driver of the transmitter according to a common mode noise signature of a common mode signal derived from the differential output.
Abstract translation: 描述了一种装置，包括：耦合到发射机的预驱动器，所述发射机具有差分输出; 以及调谐电路，其可操作以耦合到差分输出端，以根据从差分输出得到的共模信号的共模噪声特征来调谐发射机的预驱动器。
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公开(公告)号：US20160079747A1
公开(公告)日：2016-03-17
申请号：US14483649
申请日：2014-09-11
Applicant: Intel Corporation
Inventor： Amit Kumar Srivastava , KARTHIK NS , RAGHAVENDRA DEVAPPA SHARMA , DHARMARAY NEDALGI , PRASAD BHILAWADI
IPC: H02H3/00
CPC classification number: H02H3/18 , G06F1/26 , G06F1/3212 , H04B1/38 , H04L25/0272
Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.
Abstract translation: 描述了一种装置，其包括：一个或多个信号线; 耦合到所述一个或多个信号线的收发器; 以及偏置产生电路，用于为收发器提供一个或多个偏置电压，以根据一个或多个信号线的信号属性对收发器进行三态化。
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78.发明授权公开(公告)号：US12229073B2
公开(公告)日：2025-02-18
申请号：US17340315
申请日：2021-06-07
Applicant: Intel Corporation
Inventor： Amit Kumar Srivastava , Divya Gupta , Michael Karas , James Mitchell , Malay Trivedi , Chung-Chi Wang
Abstract: In one embodiment, an apparatus includes: a plurality of cores to execute instructions; a firmware agent to execute a first firmware; a Peripheral Component Interconnect Express (PCIe) interface to communicate with a device via a PCIe link; and a boot agent coupled to the PCIe interface to download the PCIe firmware from a non-volatile memory and provide the PCIe firmware to the PCIe interface. The PCIe interface may receive a PCIe firmware for the PCIe interface before the firmware agent is to receive the first firmware. Other embodiments are described and claimed.
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公开(公告)号：US20240281403A1
公开(公告)日：2024-08-22
申请号：US18648648
申请日：2024-04-29
Applicant: Intel Corporation
Inventor： Janusz Jurski , Enrico David Carrieri , Amit Kumar Srivastava , Matthew A. Schnoor , Myron Loewen
IPC: G06F13/42 , G06F9/54 , G06F13/24 , G06F13/362
CPC classification number: G06F13/4291 , G06F9/542 , G06F13/24 , G06F13/362
Abstract: Embodiments of the present disclosure may relate to apparatus, process, or techniques in a I3C protocol environment that include identifying a pending read notification message by a slave device to be sent to a master device to indicate that the data is available to be read by the master device from a buffer associated with the slave device. The pending read notification may be subsequently transmitted to the master device. Subsequently, until the data in the buffer has been read by the master device, the slave device may wait an identified amount of time that is less than a value of a timeout of the master device, and retransmit the pending read notification message to the master device. Other embodiments may be described and/or claimed.
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公开(公告)号：US12013806B2
公开(公告)日：2024-06-18
申请号：US17128384
申请日：2020-12-21
Applicant: Intel Corporation
Inventor： Janusz Jurski , Enrico David Carrieri , Amit Kumar Srivastava , Matthew A. Schnoor , Myron Loewen
IPC: G06F13/42 , G06F9/54 , G06F13/24 , G06F13/362
CPC classification number: G06F13/4291 , G06F9/542 , G06F13/24 , G06F13/362
Abstract: Embodiments of the present disclosure may relate to apparatus, process, or techniques in a I3C protocol environment that include identifying a pending read notification message by a slave device to be sent to a master device to indicate that the data is available to be read by the master device from a buffer associated with the slave device. The pending read notification may be subsequently transmitted to the master device. Subsequently, until the data in the buffer has been read by the master device, the slave device may wait an identified amount of time that is less than a value of a timeout of the master device, and retransmit the pending read notification message to the master device. Other embodiments may be described and/or claimed.
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