公开(公告)号：US11942516B2

公开(公告)日：2024-03-26

申请号：US17704906

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/12 ,  B82Y10/00 ,  G06N10/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/311 ,  H01L21/324 ,  H01L23/46 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/43 ,  H01L29/66 ,  H01L29/76 ,  H01L29/778 ,  H01L29/78 ,  H01L29/82

CPC classification number: H01L29/127 ,  B82Y10/00 ,  G06N10/00 ,  H01L21/28158 ,  H01L23/46 ,  H01L29/1033 ,  H01L29/401 ,  H01L29/423 ,  H01L29/42312 ,  H01L29/42364 ,  H01L29/437 ,  H01L29/66439 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66977 ,  H01L29/7613 ,  H01L29/7831 ,  H01L29/7845 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/324 ,  H01L29/66431 ,  H01L29/778 ,  H01L29/7782 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.

公开(公告)号：US11699747B2

公开(公告)日：2023-07-11

申请号：US16365018

申请日：2019-03-26

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Sarah Atanasov ,  Ravi Pillarisetty ,  Lester Lampert ,  James S. Clarke ,  Nicole K. Thomas ,  Roman Caudillo ,  Kanwaljit Singh ,  David J. Michalak ,  Jeanette M. Roberts ,  Stephanie A. Bojarski

IPC: H01L29/423 ,  G06N10/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/76 ,  B82Y10/00 ,  H01L29/775

CPC classification number: H01L29/775 ,  B82Y10/00 ,  G06N10/00 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/66439 ,  H01L29/66977 ,  H01L29/7613 ,  H01L29/7831

Abstract: Disclosed herein are quantum dot devices with multiple layers of gate metal, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; an insulating material above the quantum well stack, wherein the insulating material includes a trench; and a gate on the insulating material and extending into the trench, wherein the gate includes a first gate metal in the trench and a second gate metal above the first gate metal.

公开(公告)号：US11594599B2

公开(公告)日：2023-02-28

申请号：US16317023

申请日：2016-08-10

Applicant: Intel Corporation

Inventor： James S. Clarke ,  Robert L. Bristol ,  Ravi Pillarisetty ,  Jeanette M. Roberts ,  Hubert C. George ,  Nicole K. Thomas

IPC: H01L29/12 ,  H01L29/66 ,  H01L29/778 ,  H01L29/82 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/06 ,  H01L29/165 ,  H01L29/76

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; a plurality of gates disposed above the quantum well stack, wherein at least two of the gates are spaced apart in a first dimension above the quantum well stack, at least two of the gates are spaced apart in a second dimension above the quantum well stack, and the first and second dimensions are perpendicular; and an insulating material disposed above the quantum well stack, wherein the insulating material extends between at least two of the gates spaced apart in the first dimension, and the insulating material extends between at least two of the gates spaced apart in the second dimension.

公开(公告)号：US11444188B2

公开(公告)日：2022-09-13

申请号：US16648402

申请日：2017-12-21

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Nicole K. Thomas ,  Hubert C. George ,  Jeanette M. Roberts ,  Payam Amin ,  Zachary R. Yoscovits ,  Roman Caudillo ,  James S. Clarke

IPC: H01L29/778 ,  H01L29/12 ,  H01L21/321 ,  H01L21/8234 ,  H01L29/165 ,  H01L29/66 ,  H01L29/76 ,  H01L29/82 ,  B82Y10/00 ,  B82Y40/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; an insulating material at least partially above the fin, wherein the insulating material includes a trench above the fin; and a gate metal on the insulating material and extending into the trench.

公开(公告)号：US20220147858A1

公开(公告)日：2022-05-12

申请号：US17583264

申请日：2022-01-25

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Hubert C. George ,  Jeanette M. Roberts ,  Nicole K. Thomas ,  James S. Clarke

IPC: G06N10/40 ,  H01L33/50 ,  H01L33/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a base and a fin extending away from the base and including a quantum well layer. The device may further include a first gate disposed on a first side of the fin and a second gate disposed on a second side of the fin, different from the first side. Providing gates on different sides of a fin advantageously allows increasing the number of quantum dots which may be independently formed and manipulated in the fin. The quantum dots formed in such a device may be constrained in the x-direction by the one or more gates, in the y-direction by the fin, and in the z-direction by the quantum well layer, as discussed in detail herein. Methods for fabricating such devices are also disclosed.

公开(公告)号：US20210036110A1

公开(公告)日：2021-02-04

申请号：US16648442

申请日：2017-12-17

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  James S. Clarke ,  Jessica M. Torres ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Payam Amin ,  Hubert C. George ,  Jeanette M. Roberts ,  Roman Caudillo ,  David J. Michalak ,  Zachary R. Yoscovits ,  Lester Lampert

IPC: H01L29/12 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.

公开(公告)号：US10910488B2

公开(公告)日：2021-02-02

申请号：US16019334

申请日：2018-06-26

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Lester Lampert ,  James S. Clarke ,  Ravi Pillarisetty ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Roman Caudillo ,  Kanwaljit Singh ,  David J. Michalak ,  Jeanette M. Roberts

IPC: H01L29/775 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L29/12 ,  H01L29/40 ,  H01L29/76 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/778 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin has a first side face and a second side face, and the fin includes a quantum well layer; and a gate above the fin, wherein the gate extends down along the first side face.

公开(公告)号：US10804383B2

公开(公告)日：2020-10-13

申请号：US16318527

申请日：2016-09-24

Applicant: Intel Corporation

Inventor： Hubert C. George

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  B82Y40/00 ,  H01L29/12 ,  G06N10/00 ,  H01L27/085 ,  H01L29/417 ,  B82Y10/00 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3105

Abstract: Disclosed herein are single electron transistor (SET) devices, and related methods and devices. In some embodiments, a SET device may include: first and second source/drain (S/D) electrodes disposed on a side face of a first insulating support and on a side face of a second insulating support, respectively; an island disposed between the first and second S/D electrodes and extending into an area between the first and second insulating supports. In some embodiments, a SET device may include: first and second S/D electrodes disposed on a substrate; an island disposed in an area between the first and second S/D electrodes; first and second portions of dielectric disposed between the island and the first and second S/D electrodes, respectively; and a third portion of dielectric disposed between the substrate and the island.

公开(公告)号：US10770545B2

公开(公告)日：2020-09-08

申请号：US16314788

申请日：2016-08-30

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Ravi Pillarisetty ,  Jeanette M. Roberts ,  Nicole K. Thomas ,  James S. Clarke

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/778 ,  H01L29/10 ,  H01L29/423 ,  H01L29/76 ,  H01L29/165 ,  H01L29/12 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/16 ,  G06N10/00 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; an insulating material disposed above the quantum well stack, wherein the insulating material includes a trench; and a gate metal disposed on the insulating material and extending into the trench.

公开(公告)号：US10763347B2

公开(公告)日：2020-09-01

申请号：US16349955

申请日：2016-12-14

Applicant: Intel Corporation

Inventor： Payam Amin ,  Nicole K. Thomas ,  James S. Clarke ,  Jessica M. Torres ,  Ravi Pillarisetty ,  Hubert C. George ,  Kanwaljit Singh ,  Van H. Le ,  Jeanette M. Roberts ,  Roman Caudillo ,  Zachary R. Yoscovits ,  David J. Michalak

IPC: H01L29/775 ,  G06N10/00 ,  H01L21/02 ,  H01L29/12 ,  H01L29/165 ,  H01L29/66 ,  H01L29/06 ,  H01L29/76 ,  H01L29/423 ,  H01L29/40 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/778 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include: a quantum well stack having alternatingly arranged relaxed and strained layers; and a plurality of gates disposed above the quantum well stack to control quantum dot formation in the quantum well stack.