公开(公告)号：US20070259127A1

公开(公告)日：2007-11-08

申请号：US11416986

申请日：2006-05-02

申请人： Yoshi Ono ,  Bruce Ulrich ,  Wei-Wei Zhuang ,  Douglas Tweet

发明人： Yoshi Ono ,  Bruce Ulrich ,  Wei-Wei Zhuang ,  Douglas Tweet

IPC分类号： B05D5/06 ,  B05D3/12 ,  B05D3/02 ,  H05H1/00

CPC分类号： G02B3/0012 ,  H01L27/14627

摘要： A method for densifying sol-gel films to form microlens structures includes preparing a sol-gel precursor, having at least one solvent therein. The sol-gel precursor is spin coated onto a wafer to form a sol-gel film thereon. The wafer and sol-gel film are hot plate baked at a temperature less than 200° C. to remove at least some of the solvent. The baked, wafer and spin-coated sol-gel film are treated with an oxygen plasma treatment to remove any remaining solvent and to densify the sol-gel film. The spin coating, hot plate baking and treating steps may be repeated as required. A microlens is formed from the densified sol-gel film.

摘要翻译： 用于致密化溶胶 - 凝胶膜以形成微透镜结构的方法包括制备其中具有至少一种溶剂的溶胶 - 凝胶前体。 将溶胶 - 凝胶前体旋涂在晶片上以在其上形成溶胶 - 凝胶膜。 将晶片和溶胶 - 凝胶膜在低于200℃的温度下进行热板烘烤以除去至少一些溶剂。 用氧等离子体处理烘烤，晶片和旋涂溶胶 - 凝胶膜以除去任何残留的溶剂并致密化溶胶 - 凝胶膜。 可以根据需要重复旋涂，热板烘烤和处理步骤。 从致密化的溶胶 - 凝胶膜形成微透镜。

公开(公告)号：US20070105056A1

公开(公告)日：2007-05-10

申请号：US11270701

申请日：2005-11-08

申请人： Yoshi Ono ,  Bruce Ulrich

发明人： Yoshi Ono ,  Bruce Ulrich

IPC分类号： G02F7/00 ,  G02B3/00

CPC分类号： G02B3/0018 ,  G02B3/0056

摘要： A method of forming a microlens array includes preparing a substrate; fabricating a photosensitive array on the substrate; depositing a layer of lens material on the photosensitive array; depositing and patterning photoresist on the lens material, wherein patterning includes forming a photoresist region having a solid curved upper surface and a substantially rectangular base on the lens material layer; developing the photoresist; reflowing the photoresist; and processing the lens material for form a microlens array.

摘要翻译： 形成微透镜阵列的方法包括制备基底; 在基板上制造光敏阵列; 在光敏阵列上沉积一层透镜材料; 在透镜材料上沉积和图案化光刻胶，其中图案化包括在透镜材料层上形成具有实心弯曲上表面和基本上矩形基底的光致抗蚀剂区域; 显影光刻胶; 回流光刻胶; 并处理透镜材料以形成微透镜阵列。

公开(公告)号：US07129552B2

公开(公告)日：2006-10-31

申请号：US10677006

申请日：2003-09-30

申请人： Wei Gao ,  Yoshi Ono

发明人： Wei Gao ,  Yoshi Ono

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/66583 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78

摘要： MOSFET gate structures are provided comprising a niobium monoxide gate, overlying a gate dielectric. The niobium monoxide gate may have a low work function suitable for use as an NMOS gate.

摘要翻译： 提供包括覆盖栅极电介质的铌氧化物栅极的MOSFET栅极结构。 铌氧化物栅可能具有适合用作NMOS栅极的低功函数。

公开(公告)号：US20060211267A1

公开(公告)日：2006-09-21

申请号：US11418273

申请日：2006-05-04

申请人： Pooran Joshi ,  Tingkai Li ,  Yoshi Ono ,  Apostolos Voutsas ,  John Hartzell

发明人： Pooran Joshi ,  Tingkai Li ,  Yoshi Ono ,  Apostolos Voutsas ,  John Hartzell

IPC分类号： H01L21/31

CPC分类号： H01L21/31608 ,  C23C16/30 ,  C23C16/401 ,  C23C16/402 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/0234

摘要： A method is provided for forming a silicon oxide (SiOx) thin-film with embedded nanocrystalline silicon (Si). The method deposits SiOx, where x is in the range of 1 to 2, overlying a substrate, using a high-density (HD) plasma-enhanced chemical vapor deposition (PECVD) process. As a result, the SiOx thin-film is embedded with nanocrystalline Si. The HD PECVD process may use an inductively coupled plasma (ICP) source, a substrate temperature of less than about 400° C., and an oxygen source gas with a silicon precursor. In one aspect, a hydrogen source gas and an inert gas are used, where the ratio of oxygen source gas to inert gas is in the range of about 0.02 to 5. The SiOx thin-film with embedded nanocrystalline Si typically has a refractive index in the range of about 1.6 to 2.2, with an extinction coefficient in the range of 0 to 0.5.

公开(公告)号：US20060180816A1

公开(公告)日：2006-08-17

申请号：US11058505

申请日：2005-02-14

申请人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Hsu

发明人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Hsu

IPC分类号： H01L29/26

CPC分类号： H05B33/145

摘要： A method is provided for forming a Si electroluminescence (EL) device for emitting light at short wavelengths. The method comprises: providing a substrate; forming a first insulator layer overlying the substrate; forming a silicon-rich silicon oxide (SRSO) layer overlying the first insulator layer, embedded with nanocrystalline Si having a size in the range of 0.5 to 5 nm; forming a second insulator layer overlying the SRSO layer; and, forming a top electrode. Typically, the SRSO has a Si richness in the range of 5 to 40%. In one aspect, the SRSO layer is formed using a DC sputtering process. In another aspect, the SRSO formation step includes a rapid thermal annealing (RTA) process subsequent to depositing the SRSO. Likewise, thermal oxidation or plasma oxidation can be performed subsequent to the SRSO layer deposition. The size of Si nanocrystals is decreased in response to above-mentioned deposition, annealing, and oxidation processes.

摘要翻译： 提供一种用于形成用于发射短波长的光的Si电致发光（EL）装置的方法。 该方法包括：提供衬底; 形成覆盖所述衬底的第一绝缘体层; 形成覆盖在第一绝缘体层上的富硅氧化物（SRSO）层，其中嵌入尺寸在0.5至5nm范围内的纳米晶体Si; 形成覆盖所述SRSO层的第二绝缘体层; 并形成顶部电极。 通常，SRSO的Si浓度范围为5〜40％。 在一个方面，使用DC溅射工艺形成SRSO层。 另一方面，SRSO形成步骤包括在沉积SRSO之后的快速热退火（RTA）工艺。 同样地，可以在SRSO层沉积之后进行热氧化或等离子体氧化。 响应于上述沉积，退火和氧化过程，Si纳米晶体的尺寸减小。

公开(公告)号：US20060160335A1

公开(公告)日：2006-07-20

申请号：US11039463

申请日：2005-01-19

申请人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Hsu

发明人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Hsu

IPC分类号： H01L21/20

CPC分类号： C23C14/16 ,  C03C17/34 ,  C23C14/10 ,  C23C28/322 ,  C23C28/323 ,  C23C28/345 ,  C23C28/3455 ,  C23C28/42 ,  H01L21/02164 ,  H01L21/02266 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0259 ,  H01L21/02631 ,  H01L21/02667 ,  H01L21/31608 ,  H01L33/26

摘要： Provided are an electroluminescence (EL) device and corresponding method for forming a rare earth element-doped silicon (Si)/Si dioxide (SiO2) lattice structure. The method comprises: providing a substrate; DC sputtering a layer of amorphous Si overlying the substrate; DC sputtering a rare earth element; in response, doping the Si layer with the rare earth element; DC sputtering a layer of SiO2 overlying the rare earth-doped Si; forming a lattice structure; annealing; and, in response to the annealing, forming nanocrystals in the rare-earth doped Si having a grain size in the range of 1 to 5 nanometers (nm). In one aspect, the rare earth element and Si are co-DC sputtered. Typically, the steps of DC sputtering Si, DC sputtering the rare earth element, and DC sputtering the SiO2 are repeated 5 to 60 cycles, so that the lattice structure includes the plurality (5-60) of alternating SiO2 and rare earth element-doped Si layers.

摘要翻译： 提供了一种用于形成稀土元素掺杂硅（Si）/二氧化硅（SiO 2）晶格结构的电致发光（EL）器件和相应的方法。 该方法包括：提供衬底; DC溅射覆盖衬底的非晶硅层; 直流溅射稀土元素; 作为响应，用稀土元素掺杂Si层; DC溅射一层SiO 2，覆盖稀土掺杂的Si; 形成晶格结构; 退火; 并且响应于退火，在具有1至5纳米（nm）范围内的晶粒尺寸的稀土掺杂Si中形成纳米晶体。 一方面，稀土元素和Si共溅射。 通常，DC溅射Si，DC溅射稀土元素和DC溅射SiO 2的步骤重复5至60个循环，使得晶格结构包括多个（5-60）交替的SiO 2和稀土元素掺杂 Si层。

公开(公告)号：US20060046204A1

公开(公告)日：2006-03-02

申请号：US10931596

申请日：2004-08-31

申请人： Yoshi Ono ,  Wei-Wei Zhuang ,  Wei Gao ,  Bruce Ulrich

发明人： Yoshi Ono ,  Wei-Wei Zhuang ,  Wei Gao ,  Bruce Ulrich

IPC分类号： G02B3/00

CPC分类号： G02B3/0012

摘要： A method of forming a microlens structure using a patternable lens material is provided. An organic-inorganic hybrid polymer comprising titanium dioxide is exposed to light using a defocused mask image and then developed to produce a lens-shaped region.

摘要翻译： 提供了使用可图案的透镜材料形成微透镜结构的方法。 使用散焦的掩模图像将包含二氧化钛的有机 - 无机杂化聚合物暴露于光，然后显影以产生透镜形区域。

公开(公告)号：US20050136695A1

公开(公告)日：2005-06-23

申请号：US11046571

申请日：2005-01-28

申请人： Pooran Joshi ,  John Hartzell ,  Masahiro Adachi ,  Yoshi Ono

发明人： Pooran Joshi ,  John Hartzell ,  Masahiro Adachi ,  Yoshi Ono

IPC分类号： H01L21/316 ,  H01L21/336 ,  H01L29/49 ,  H01L29/786 ,  H01L23/58 ,  H01L21/26 ,  H01L21/324 ,  H01L21/42 ,  H01L21/477

CPC分类号： H01L29/66757 ,  H01L29/4908 ,  H01L29/66772

摘要： An oxide interface and a method for fabricating an oxide interface are provided. The method comprises forming a silicon layer and an oxide layer overlying the silicon layer. The oxide layer is formed at a temperature of less than 400° C. using an inductively coupled plasma source. In some aspects of the method, the oxide layer is more than 20 nanometers (nm) thick and has a refractive index between 1.45 and 1.47. In some aspects of the method, the oxide layer is formed by plasma oxidizing the silicon layer, producing plasma oxide at a rate of up to approximately 4.4 nm per minute (after one minute). In some aspects of the method, a high-density plasma enhanced chemical vapor deposition (HD-PECVD) process is used to form the oxide layer. In some aspects of the method, the silicon and oxide layers are incorporated into a thin film transistor.

摘要翻译： 提供氧化物界面和制造氧化物界面的方法。 该方法包括形成硅层和覆盖硅层的氧化物层。 使用电感耦合等离子体源在低于400℃的温度下形成氧化物层。 在该方法的一些方面，氧化物层的厚度大于20纳米（nm），折射率在1.45和1.47之间。 在该方法的一些方面，通过等离子体氧化硅层形成氧化物层，以每分钟高达约4.4nm的速率产生等离子体氧化物（1分钟后）。 在该方法的某些方面，使用高密度等离子体增强化学气相沉积（HD-PECVD）工艺来形成氧化物层。 在该方法的一些方面，将硅和氧化物层结合到薄膜晶体管中。

公开(公告)号：US20050088898A1

公开(公告)日：2005-04-28

申请号：US10976596

申请日：2004-10-29

申请人： Sheng Hsu ,  Yoshi Ono

发明人： Sheng Hsu ,  Yoshi Ono

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： H01L21/28194 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7883 ,  Y10S438/975

摘要： Flash memory cells are provided with a high-k material interposed between a floating polysilicon gate and a control gate. A tunnel oxide is interposed between the floating polysilicon gate and a substrate. Methods of forming flash memory cells are also provided comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. A high-k dielectric layer may then be deposited over the first polysilicon layer. A third polysilicon layer may then be deposited over the high-k dielectric layer and patterned using photoresist to form a flash memory gate structure. During patterning, exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer. A thin layer of the first polysilicon layer remains, to be carefully removed using a subsequent selective etch process. The high-k dielectric layer may be patterned to allow for formation of non-memory transistors in conjunction with the process of forming the flash memory cells.

摘要翻译： 闪存单元设置有插入在浮置多晶硅栅极和控制栅极之间的高k材料。 在浮置多晶硅栅极和衬底之间插入隧道氧化物。 还提供了形成闪存单元的方法，包括在衬底上形成第一多晶硅层。 通过第一多晶硅层形成沟槽并进入衬底，并用氧化物层填充沟槽。 在氧化物上沉积第二多晶硅层，使得沟槽内的第二多晶硅层的底部高于第一多晶硅层的底部，并且沟槽内的第二多晶硅层的顶部低于第一多晶硅的顶部 层。 然后可以使用CMP工艺将得到的结构平坦化。 然后可以在第一多晶硅层上沉积高k电介质层。 然后可以在高k电介质层上沉积第三多晶硅层，并使用光致抗蚀剂图案化以形成闪存栅极结构。 在图案化期间，蚀刻暴露的第二多晶硅层。 在完成去除第二多晶硅层时检测到蚀刻停止。 保留第一多晶硅层的薄层，使用随后的选择性蚀刻工艺小心地去除。 结合形成闪速存储器单元的过程，高k电介质层可以被图案化以允许形成非存储晶体管。

公开(公告)号：US06468901B1

公开(公告)日：2002-10-22

申请号：US09847873

申请日：2001-05-02

申请人： Jer-shen Maa ,  Yoshi Ono ,  Fengyan Zhang

发明人： Jer-shen Maa ,  Yoshi Ono ,  Fengyan Zhang

IPC分类号： H01L2144

CPC分类号： H01L21/28518

摘要： An integrated circuit device, and a method of manufacturing the same, including nickel silicide on a silicon substrate fabricated with an iridium interlayer. In one embodiment the method comprises depositing an iridium (Ir) interface layer between the Ni and Si layers prior to the silicidation reaction. The thermal stability is much improved by adding the thin iridium layer. This is shown by the low junction leakage current of the ultra-shallow junction, and by the low sheet resistance of the silicide, even after annealing at 850° C.

摘要翻译： 一种集成电路器件及其制造方法，包括用铱中间层制造的硅衬底上的硅化镍。 在一个实施方案中，该方法包括在硅化反应之前在Ni和Si层之间沉积铱（Ir）界面层。 通过添加薄铱层，热稳定性大大提高。 即使在850℃退火之后，超浅结的低结漏电流和硅化物的薄片电阻也被示出。