公开(公告)号：US4620872A

公开(公告)日：1986-11-04

申请号：US787529

申请日：1985-10-15

申请人： Kenichi Hijikata ,  Katsuyuki Sato ,  Hitoshi Maruyama ,  Ryoko Furuhashi

发明人： Kenichi Hijikata ,  Katsuyuki Sato ,  Hitoshi Maruyama ,  Ryoko Furuhashi

IPC分类号： B22F1/00 ,  B22F3/14 ,  C22C1/04 ,  G11B11/105 ,  H01F10/12 ,  H01F41/18 ,  C22C19/07 ,  B22F3/00 ,  C22C38/00

CPC分类号： B22F1/0003 ,  B22F3/14 ,  C22C1/0441 ,  G11B11/10586 ,  H01F41/183

摘要： A novel composite target material that is composed of a rare earth metal and a transition metal (iron-group metal) and which is used in the formation of a thin magnetooptical recording film by sputtering is disclosed. Also disclosed is a process for producing such composite target material.The process comprises the steps of providing a rare earth metal and an iron-group transition metal as separate entities, mixing these metals without alloying, and hot-forming the mixture at a temperature lower than the eutectic point of the system of metallic components in the mixture, thereby forming an intermetallic compound at the interface between the rare earth metal and the transition metal while causing said metals to be bonded together.The target material produced by this process contains 30-50 wt % of the rare earth metal, with the balance being made of the iron-group transition metal and incidental impurities. The structure of the target material is also characterized by the presence of an intermetallic compound phase at the interface between the particles of the rare earth metal and those of the transition metal. This composite target material has sufficiently high density, high strength, high deflective strength and good resistance to thermal shock to permit rotation and inversion during sputtering procedures without cracking. Furthermore, the oxygen content of this target material is no higher than 0.3 wt %. Therefore, a perpendicular magnetization film suitable for use in magnetooptical recording can be readily formed by sputtering the target material of the present invention. As a further advantage, the film deposition rate that can be achieved with this target material is significantly fast in comparison with the conventional alloy target material.

摘要翻译： 公开了一种由稀土金属和过渡金属（铁族金属）组成并用于通过溅射形成薄磁光记录膜的新型复合靶材料。 还公开了制造这种复合靶材的方法。 该方法包括以下步骤：提供稀土金属和铁基过渡金属作为单独的实体，将这些金属混合而不合金化，并在低于金属组分体系的共晶点的温度下热成型混合物 从而在稀土金属和过渡金属之间的界面处形成金属间化合物，同时使所述金属结合在一起。 通过该方法制造的目标材料含有30-50重量％的稀土金属，余量由铁基过渡金属和杂质构成。 目标材料的结构的特征还在于在稀土金属颗粒与过渡金属的颗粒之间的界面存在金属间化合物相。 该复合靶材料具有足够高的密度，高强度，高的偏转强度和良好的耐热冲击性，以允许溅射过程中的旋转和反转而不发生裂纹。 此外，该目标材料的氧含量不高于0.3重量％。 因此，通过溅射本发明的靶材料可以容易地形成适用于磁光记录的垂直磁化膜。 另外的优点是，与常规的合金靶材相比，用该目标材料可以实现的成膜速度显着快。

公开(公告)号：US09860901B2

公开(公告)日：2018-01-02

申请号：US13033383

申请日：2011-02-23

申请人： Katsuyuki Sato

发明人： Katsuyuki Sato

IPC分类号： H04L27/00 ,  G10L19/00 ,  H04L27/04 ,  H04N5/38 ,  H04W72/04

CPC分类号： H04W72/0486

摘要： A transmission device includes: a communication unit that communicates with a plurality of reception devices; a transmission data setting unit that compares the number of the reception devices as transmission targets of transmission data representing content and a predetermined threshold value and sets the transmission data to be transmitted to the reception devices to each reception device based on a result of the comparison such that a transmission rate for transmission that represents an amount of data transmission necessary to transmit the transmission data to the reception devices does not exceed a reference transmission rate representing an amount of data transmission at which data can be transmitted in the communication, and the transmission data having relatively high reproduction quality is transmitted to the reception devices as the transmission targets; and a transmission processing unit that concurrently transmits the transmission data set by the transmission data setting unit to the corresponding reception devices as the transmission targets.

公开(公告)号：US5629898A

公开(公告)日：1997-05-13

申请号：US607977

申请日：1996-02-29

申请人： Youji Idei ,  Katsuhiro Shimohigashi ,  Masakazu Aoki ,  Hiromasa Noda ,  Katsuyuki Sato ,  Hidetoshi Iwai ,  Makoto Saeki ,  Jun Murata ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Osamu Tsuchiya

发明人： Youji Idei ,  Katsuhiro Shimohigashi ,  Masakazu Aoki ,  Hiromasa Noda ,  Katsuyuki Sato ,  Hidetoshi Iwai ,  Makoto Saeki ,  Jun Murata ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Osamu Tsuchiya

IPC分类号： G11C11/406 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C2211/4016 ,  G11C2211/4061

摘要： A period pulse corresponding to the shortest information retention time of those of dynamic memory cells is counted to form a refresh address to be assigned to a plurality of word lines. A carry signal outputted from the refresh address counter is divided by a divider. For each of said plurality of word lines assigned with the refresh address, one of a short period corresponding to an output pulse of a timer or a long period corresponding to the divided pulse from the divider is stored in a storage circuit as refresh time setting information. A memory cell refresh operation to be performed by the refresh address is made valid or invalid for each word line according to the refresh time setting information stored in the storage circuit and the refresh time setting information itself is made invalid by the output pulse of the divider.

摘要翻译： 对与动态存储单元的最短信息保持时间对应的周期脉冲进行计数，以形成分配给多个字线的刷新地址。 从刷新地址计数器输出的进位信号由分频器分频。 对于分配有刷新地址的所述多个字线中的每一个，对应于定时器的输出脉冲的短周期中的一个或与来自分频器的分频脉冲相对应的长周期中的一个作为刷新时间设置信息被存储在存储电路中 。 根据存储在存储电路中的刷新时间设定信息，由刷新地址执行的存储器单元刷新动作对每个字线进行有效或无效，并且刷新时间设定信息本身被分频器的输出脉冲无效 。

公开(公告)号：US5463249A

公开(公告)日：1995-10-31

申请号：US982169

申请日：1992-11-24

申请人： Yutaka Shinbo ,  Takeshi Kajimoto ,  Mitsuteru Kobayashi ,  Katsuyuki Sato

发明人： Yutaka Shinbo ,  Takeshi Kajimoto ,  Mitsuteru Kobayashi ,  Katsuyuki Sato

IPC分类号： H01L21/822 ,  G11C5/00 ,  H01L23/538 ,  H01L25/18 ,  H01L27/04 ,  H01L23/48 ,  H01L29/44 ,  H01L29/52 ,  H01L29/60

CPC分类号： H01L25/18 ,  H01L23/5385 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165

摘要： In an electronic circuit system unit having a semiconductor integrated circuit unit on a wafer scale, a semiconductor wafer (a semiconductor integrated circuit unit on a wafer scale) and a print wiring substrate are laid to overlap each other and semiconductor pellets are mounted on the print wiring substrate in the overlapping area of the print wiring substrate and the semiconductor wafer. In said electronic circuit system unit, an area being a part of the periphery of the semiconductor wafer is protruded from the periphery of the print wiring substrate being placed to overlap the semiconductor wafer, and the semiconductor wafer and the print wiring substrate are electrically connected to each other in an area being a part of the protruded part through wires.

摘要翻译： 在具有晶片尺寸上的半导体集成电路单元的电子电路系统单元中，放置半导体晶片（晶片上的半导体集成电路单元）和印刷布线基板以彼此重叠，将半导体芯片安装在打印机 布线基板在印刷布线基板和半导体晶片的重叠区域中。 在所述电子电路系统单元中，作为半导体晶片的周边的一部分的区域从被布置为与半导体晶片重叠的印刷布线基板的周边突出，并且半导体晶片和印刷布线基板电连接到 在通过导线的突出部分的一个区域中彼此相对。

公开(公告)号：US5420824A

公开(公告)日：1995-05-30

申请号：US180510

申请日：1994-01-12

申请人： Takeshi Kajimoto ,  Mitsuteru Kobayashi ,  Katsuyuki Sato ,  Yutaka Shimbo

发明人： Takeshi Kajimoto ,  Mitsuteru Kobayashi ,  Katsuyuki Sato ,  Yutaka Shimbo

IPC分类号： G11C29/00 ,  G11C11/401 ,  G11C11/408 ,  G11C11/409 ,  G11C11/411 ,  G11C29/04 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  G11C13/00

CPC分类号： G11C29/70 ,  G11C29/76

摘要： In LSI circuit devices having a plurality of subchips packaged therein and having specific functions, capacitance cutting buffer circuits are employed in conjunction with respective terminals of the subchips, and a driver is disposed at respective points where relatively long wiring lines are respectively sub-divided into a corresponding plurality of lines. As a result, signal transmission delay can be significantly reduced. The terminals of the subchips are also provided with a probing pad to test the operations of the subchips independently of one another. The subchips employ circuit blocks which are to operate simultaneously and in conjunction with the wirings of the subchips, power supply lines are disposed correspondingly to the distributively arranged circuit blocks. Bus lines also controllably transmit addresses as well as data signals in a time sharing manner. Furthermore, each of the subchips has a fault test circuit. The subchips which have a DC fault is electrically isolated thereby allowing the remainder of the subchip to be usable. In the fault relieving technique employed, a combination of memory locations wherein no fault exists is selected for use, thereby allowing the construction of an LSI even with subchips which correspond to faulty bit addresses. The fault relieving technique employed uses an address converting circuit for faulty addresses, this operation being performed automatically within the chip system.

摘要翻译： 在具有封装在其中并具有特定功能的多个子芯片的LSI电路装置中，与子芯片的各个端子一起使用电容切割缓冲电路，并且驱动器设置在相对较长的布线分别分为 相应的多行。 结果，可以显着地减少信号传输延迟。 子芯片的端子还设有探测板，以独立于彼此测试子芯片的操作。 子芯片采用同时操作并与子芯片的布线一起工作的电路块，电源线相对于分布式布置的电路块设置。 总线也可以以时间分配方式可控地发送地址以及数据信号。 此外，每个子芯片具有故障测试电路。 具有DC故障的子芯片被电隔离，从而允许子芯片的其余部分可用。 在采用的故障消除技术中，选择存在无故障的存储器位置的组合，从而即使使用与故障位地址相对应的子芯片也可以构造LSI。 所采用的故障消除技术使用地址转换电路用于故障地址，该操作在芯片系统内自动执行。

公开(公告)号：US5311476A

公开(公告)日：1994-05-10

申请号：US943341

申请日：1992-06-18

申请人： Takeshi Kajimoto ,  Yutaka Shimbo ,  Katsuyuki Sato ,  Masahiro Ogata ,  Kanehide Kenmizaki ,  Shouji Kubono ,  Nobuo Kato ,  Kiichi Manita ,  Michitaro Kanamitsu

发明人： Takeshi Kajimoto ,  Yutaka Shimbo ,  Katsuyuki Sato ,  Masahiro Ogata ,  Kanehide Kenmizaki ,  Shouji Kubono ,  Nobuo Kato ,  Kiichi Manita ,  Michitaro Kanamitsu

IPC分类号： G01R31/26 ,  G01R31/28 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4093 ,  G11C29/00 ,  G11C29/02 ,  G11C29/14 ,  G11C29/50 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H03K3/037 ,  H03K19/096

CPC分类号： G11C29/027 ,  G11C11/406 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004

摘要： There is provided in connection with a semiconductor memory, such as of the pseudostatic RAM, a layout of the circuit components thereof including a method of testing the memory. There is provided an oscillation circuit which is capable of withstanding bumping of the power source voltage (varying) which effects stabilization regarding the operation of the circuits included therewith including a refresh timer circuit. There is also provided for testing a refresh timer circuit and a semiconductor memory which includes a refresh timer circuit. There is further provided for an output buffer which is capable of high speed operation with respect to memory data readout, a voltage generating circuit which is capable of stable operation and a fuse circuit, such as provided in connection with redundant circuitry in the memory and which is characterized as having a configuration of a fuse logic gate circuit employing complementary channel MOSFETs together with a fuse. With respect to the semiconductor memory, such as the pseudostatic RAM, the initial count of the refresh timer counter circuit of the refresh timer circuit can be set at an optional value by applying a signal to an address input terminal, and a test mode can be effected in which the refresh period can be set at an optional value by accordingly applying a test control signal to a predetermined external terminal. Therefore, the discharge current of the oscillation circuit capacitor associated with the refresh timer circuit becomes stabilized, noting the particular layout arrangement regarding the polycrystalline silicon layer forming the resistor of the oscillation circuit, and the fact that same parasitic capacitances are effectively connected between the polycrystalline silicon resistor and the supply voltage of the circuit and between the polycrystalline silicon resistor and the ground potential of the circuit thereby cancelling any variation of the output of the power source. Therefore, variation of the oscillation frequency of the oscillation circuit attributable to the bumping of the power source can be effectively suppressed.

公开(公告)号：US5157629A

公开(公告)日：1992-10-20

申请号：US336345

申请日：1989-04-10

申请人： Katsuyuki Sato ,  Hiroshi Kawamoto ,  Kazumasa Yanagisawa

发明人： Katsuyuki Sato ,  Hiroshi Kawamoto ,  Kazumasa Yanagisawa

IPC分类号： G11C11/4074 ,  G11C29/50

CPC分类号： G11C29/50016 ,  G11C11/4074 ,  G11C29/50 ,  G11C11/401 ,  G11C2029/5004

摘要： A dynamic RAM is provided with a plurality of 1-MOSFET memory cells, each having a storage capacitor and a switching MOSFET coupled to one electrode of the storage capacitor. The other electrode of each of the storage capacitors is coupled to a switching circuit which controls the voltage which is applied to the capacitor. The switching circuit is, in turn, coupled to both a voltage generating circuit (which preferably provides a voltage of 1/2 Vcc) and a voltage supply circuit which is set to provide predetermined test voltages. Thus, by operating the switching circuit, a voltage of 1/2 Vcc can be applied to the memory cell capacitors during normal operation of the dynamic RAM, and the predetermined test voltages can be applied to the memory cell capacitors during a testing operation.

摘要翻译： 动态RAM设置有多个1-MOSFET存储单元，每个具有存储电容器和耦合到存储电容器的一个电极的开关MOSFET。 每个存储电容器的另一个电极耦合到控制施加到电容器的电压的开关电路。 开关电路又耦合到电压产生电路（其优选地提供1/2Vcc的电压）和被设置为提供预定测试电压的电压供应电路两者。 因此，通过操作开关电路，在动态RAM的正常操作期间可以向存储单元电容器施加1/2Vcc的电压，并且可以在测试操作期间将预定的测试电压施加到存储单元电容器。

公开(公告)号：US4899312A

公开(公告)日：1990-02-06

申请号：US214542

申请日：1988-07-01

申请人： Katsuyuki Sato

发明人： Katsuyuki Sato

IPC分类号： G11C11/401 ,  G06F12/02 ,  G11C7/00 ,  G11C11/409 ,  G11C11/4096

CPC分类号： G11C11/4096

摘要： An improved DRAM which includes a plurality of main amplifiers for amplifying and storing signals read out to a plurality of common data lines in accordance with an internal address signal, a main amplifier control circuit for outputting the outputs of the main amplifiers sequentially in synchronism with changes in a column address strobe signal and an address counter for performing an addressing operation midway in the sequential reading operations of the plural main amplifiers. The present invention also includes a column selecting circuit for switching column switches in accordance with the address counter to cause data to be read out continuously at a high speed by extending a nibble mode.

公开(公告)号：US4873559A

公开(公告)日：1989-10-10

申请号：US253779

申请日：1988-10-05

申请人： Shinji Shimizu ,  Osamu Tsuchiya ,  Katsuyuki Sato

发明人： Shinji Shimizu ,  Osamu Tsuchiya ,  Katsuyuki Sato

IPC分类号： G11C7/18 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  G11C7/18 ,  H01L27/10805 ,  H01L29/66181 ,  Y10S257/906

摘要： Dynamic RAM having memory cells, each of the memory cells having a capacitor with the electrode comprised of a first semiconductor region of a first type of conductivity formed in a substrate of second conductivity type. The first semiconductor region is formed by introducing impurities using a mask comprising (1) a nitride film which is deposited so as to define part of the shape of the capacitor. An oxide film, formed by thermal oxidation of the substrate, defines the shape of the memory cells, and each of the memory cells further have at least a second semiconductor region of a second type of conductivity formed between and under the electrodes, the shape thereof being defined by the nitride film and the oxide film that is formed by thermal oxidation.

摘要翻译： 具有存储单元的动态RAM，每个存储单元具有电容器，该电极由在第二导电类型的衬底中形成的第一类导电体的第一半导体区域构成。 通过使用掩模引入杂质来形成第一半导体区域，所述掩模包括（1）沉积以限定电容器的形状的一部分的氮化物膜。 通过衬底的热氧化形成的氧化膜限定了存储单元的形状，并且每个存储单元还具有形成在电极之间和之下的至少第二导电类型的第二半导体区域，其形状 由氮化物膜和通过热氧化形成的氧化物膜限定。

公开(公告)号：US4780852A

公开(公告)日：1988-10-25

申请号：US878072

申请日：1986-06-24

申请人： Kazuhiko Kajigaya ,  Katsuyuki Sato

发明人： Kazuhiko Kajigaya ,  Katsuyuki Sato

IPC分类号： G11C11/401 ,  G11C11/409 ,  G11C11/4096 ,  G11C7/00

CPC分类号： G11C11/4096

摘要： A dynamic RAM is arranged such that a common data line in each of the non-selected ones of the divided memory arrays is connected to a pair of common source lines of a sense amplifier corresponding to the memory array concerned, whereby the potential of the common data line is set at a medium level which is substantially equal to the potential of the data lines by utilizing the medium potential of the pair of common source lines and a relatively large parasitic capacity thereof, therby maintaining the data lines at the half-precharge level. The pair of common source lines are shorted to each other during the non-select period of the memory arrays, so that the common source lines have a medium level which is substantially equal to the half-precharge level of the data lines.

摘要翻译： 动态RAM被布置成使得分开的存储器阵列中的每个未选择的存储器阵列中的公共数据线连接到与所涉及的存储器阵列相对应的读出放大器的一对公共源极线，由此共同的 数据线通过利用一对公共源极线的中等电位和相对较大的寄生电容而设定在基本上等于数据线的电位的中等电平，从而将数据线保持在半预充电电平 。 这些公共源极线在存储器阵列的非选择周期期间彼此短路，使得公共源极线具有基本上等于数据线的半预充电电平的中等电平。