公开(公告)号：US6144610A

公开(公告)日：2000-11-07

申请号：US294512

申请日：1999-04-20

申请人： Hua Zheng ,  Kamin Fei

发明人： Hua Zheng ,  Kamin Fei

IPC分类号： G11C8/08 ,  G11C11/408 ,  G11C7/00

CPC分类号： G11C11/4085 ,  G11C8/08

摘要： A memory device that includes a row decoder, a set of word line, and one or more word line pull-down drivers. The row decoder includes decoding circuitry and a set of word line drivers. The decoding circuitry is configured to receive address information and generate a set of word line control signals. The word line drivers couple to the decoding circuitry and are responsive to the word line control signals. Each word line driver is configured to provide pull-up drive capability, and can further be configured to provide pull-down drive capability. Each word line couples to at least one word line driver. The word line pull-down driver(s) couples to the word lines, with each word line pull-down driver being configured to provide pull-down drive capability. One or more word line pull-down drivers can be distributed (i.e., uniformly) along the length of each word line. The word lines can also be implemented using a hierarchical word line architecture that includes a set of main word lines (i.e., fabricated on a metal layer) and a set of segmented word lines (i.e., fabricated on a polysilicon layer) coupled to each main word line.

摘要翻译： 一种包括行解码器，一组字线以及一个或多个字线下拉驱动器的存储器件。 行解码器包括解码电路和一组字线驱动器。 解码电路被配置为接收地址信息并产生一组字线控制信号。 字线驱动器耦合到解码电路并且响应于字线控制信号。 每个字线驱动器被配置为提供上拉驱动能力，并且还可以被配置为提供下拉驱动能力。 每个字线耦合到至少一个字线驱动器。 字线下拉驱动器耦合到字线，每个字线下拉驱动器被配置为提供下拉驱动能力。 可以沿着每个字线的长度分布（即，均匀地）一个或多个字线下拉驱动器。 字线还可以使用包括一组主字线（即，在金属层上制造）和一组分段字线（即，在多晶硅层上制造的）的分层字线结构来实现，耦合到每个主线 字线。

公开(公告)号：US6097781A

公开(公告)日：2000-08-01

申请号：US17370

申请日：1998-02-02

申请人： Jeffrey P. Wright ,  Hua Zheng

发明人： Jeffrey P. Wright ,  Hua Zheng

IPC分类号： H03K21/00 ,  G06M3/00

CPC分类号： H03K21/00

摘要： A shared counter performs multiple counting functions in an electronic circuit, such as a memory integrated circuit. An input selection circuit selects one of M input data sets at a given time to be provided as counter initialization data. A counter circuit provides counter output data based on the counter initialization data. An output circuit provides the counter output data to K destination circuits in the electronic circuit. The output circuit provides only one of the K destination circuits with the counter output data at a given time.

公开(公告)号：US6094378A

公开(公告)日：2000-07-25

申请号：US348794

申请日：1999-07-07

申请人： Hua Zheng

发明人： Hua Zheng

IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C11/4096

CPC分类号： G11C7/1048 ,  G11C11/4096

摘要： A voltage booting circuit for booting the switching signal applied to a column access passgate is employed to reduce the voltage drop across the passgate. Reduction of the voltage dropped across the passgate results in faster read and write times and improved noise margin. In one application the booted voltage is used only during a write operation, but not during a read. In another application, the booted voltage is used during both operations.

摘要翻译： 用于引导施加到列存取通道的开关信号的电压启动电路用于减小通过门的电压降。 降低通过门口的电压降低导致更快的读取和写入时间以及改善的噪声容限。 在一个应用中，引导电压仅在写操作期间使用，但不在读取期间使用。 在另一个应用中，在两个操作期间都使用引导电压。

公开(公告)号：US6061291A

公开(公告)日：2000-05-09

申请号：US115379

申请日：1998-07-14

申请人： Hua Zheng

发明人： Hua Zheng

IPC分类号： G11C5/00 ,  G11C8/10 ,  G11C8/00

CPC分类号： G11C8/10 ,  G11C29/781 ,  G11C29/808

摘要： A memory circuit column decoder is provided with an array of fuses that can be selectively blown to indicate a fuse address of a defective column of a memory array to be substituted by a redundant column. The memory circuit column decoder also includes a decoder that receives a mask that selectively masks out certain columns of a group of columns from being written during a block write operation, and the fuse address from the array of fuses. The decoder generates a signal for disabling the redundant column during a block write operation when the mask masks out the defective column.

摘要翻译： 存储器电路列解码器设置有可选择性地熔断的熔丝阵列，以指示要由冗余列代替的存储器阵列的缺陷列的熔丝地址。 存储器电路列解码器还包括一个解码器，该解码器接收一个掩模，该掩模选择性地掩蔽一组列的某些列在块写入操作期间被写入，并且熔丝地址从保险丝阵列接收。 当掩模屏蔽缺陷列时，解码器在块写入操作期间产生用于禁用冗余列的信号。

公开(公告)号：US5917762A

公开(公告)日：1999-06-29

申请号：US13769

申请日：1998-01-27

申请人： Hua Zheng ,  Jeffrey P. Wright

发明人： Hua Zheng ,  Jeffrey P. Wright

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  H03K5/13 ,  H03K5/135 ,  G11C7/00

CPC分类号： H03K5/133 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  H03K5/135

摘要： A delay circuit provides a substantially constant delay over a range of power-supply voltages. The delay circuit includes an input terminal that receives an input signal, an output terminal that provides an output signal, and a supply terminal that receives a supply voltage. A delay stage is coupled between the input and the output terminals and, when the supply voltage has a predetermined value, generates the output signal a predetermined delay time after it receives the input signal. A control stage is coupled between the supply terminal and the delay stage and regulates the supply current that flows between the supply terminal and the delay stage such that the delay time of the delay stage remains substantially equal to the predetermined delay time as the supply voltage varies from the predetermined value.

公开(公告)号：US08782692B2

公开(公告)日：2014-07-15

申请号：US13074863

申请日：2011-03-29

申请人： Eugene Chuan-Huai Wei ,  Peter E. Sargent ,  Hua Zheng

发明人： Eugene Chuan-Huai Wei ,  Peter E. Sargent ,  Hua Zheng

IPC分类号： H04N7/10 ,  H04N7/025 ,  H04N21/222 ,  H04N21/234 ,  H04N21/235 ,  H04N21/237 ,  H04N21/24 ,  H04N21/2543 ,  H04N21/2547 ,  H04N21/435 ,  H04N21/44 ,  H04N21/442

CPC分类号： H04N21/2353 ,  G06Q30/0241 ,  H04N9/79 ,  H04N21/222 ,  H04N21/23424 ,  H04N21/237 ,  H04N21/2408 ,  H04N21/25435 ,  H04N21/2547 ,  H04N21/40 ,  H04N21/435 ,  H04N21/44016 ,  H04N21/44204 ,  H04N21/44222 ,  H04N21/47202 ,  H04N21/4826 ,  H04N21/812 ,  H04N21/8455 ,  H04N21/8549

摘要： A method, system, and computer program product provide the ability to recommend, to a first viewer, alternative programming during playback of a first media program. The first media program is played. A second media program of potential interest to the user is identified. During an advertising break, an interface is presented to the user that identifies the second media program. An indication of interest in the second media program is received from the user. If the indication indicates that the user is interested in the second media program, a reference to the second media program is saved as a viewer recommendation for later playback. If not interested, additional input may be received from the user indicating why the user is not interested.

摘要翻译： 一种方法，系统和计算机程序产品提供在第一媒体节目播放期间向第一观看者推荐替代节目的能力。 播放第一个媒体节目。 识别出对用户具有潜在兴趣的第二媒体节目。 在广告休息期间，向用户呈现标识第二媒体节目的界面。 从用户接收到对第二媒体节目感兴趣的指示。 如果该指示表示用户对第二媒体节目感兴趣，则将对第二媒体节目的引用保存为用于稍后播放的观众推荐。 如果不感兴趣，可以从用户接收到额外的输入，指示用户不感兴趣的原因。

公开(公告)号：US20130321478A1

公开(公告)日：2013-12-05

申请号：US13578622

申请日：2012-06-13

申请人： Hua Zheng ,  Cheng-hung Chen

发明人： Hua Zheng ,  Cheng-hung Chen

IPC分类号： G09G5/10

CPC分类号： G09G5/10 ,  G09G3/20 ,  G09G3/2092 ,  G09G2300/0408 ,  G09G2310/0281 ,  G09G2320/0223

摘要： The display panel includes data driven chip and at least two scanning driven chips. The second scanning signal input terminal of each of the scanning driven chip is connected to a first scanning signal output terminal of the data driven chip by corresponding transmission circuits. At least one transmission circuit includes a serially connected resistor so that sum of impedance of the transmission circuits are equal, or the difference of the impedance of the transmission circuit is less than a predetermined value. In addition, a flat-panel display device with uniform brightness and a driving method thereof are also provided.

摘要翻译： 显示面板包括数据驱动芯片和至少两个扫描驱动芯片。 每个扫描驱动芯片的第二扫描信号输入端通过相应的传输电路连接到数据驱动芯片的第一扫描信号输出端。 至少一个传输电路包括串联的电阻器，使得发送电路的阻抗之和相等，或者发送电路的阻抗差小于预定值。 此外，还提供了具有均匀亮度的平板显示装置及其驱动方法。

公开(公告)号：US20130319745A1

公开(公告)日：2013-12-05

申请号：US13519374

申请日：2012-06-11

申请人： Hua Zheng ,  Cheng-hung Chen

发明人： Hua Zheng ,  Cheng-hung Chen

IPC分类号： H05K1/11

CPC分类号： H05K1/0269 ,  H05K1/0289 ,  H05K2201/09281 ,  H05K2201/09936

摘要： The present invention provides a routing structure and display panel. The routing structure includes a plurality of routing, disposed separately. Each routing corresponds to a symbol, and the symbol is disposed on the routing to act as a part of the routing to conduct electricity. In this manner, the routing structure and display panel of the present invention allow expansion of routing width, effectively reduce RC constant and energy-consumption, and improve yield rate.

摘要翻译： 本发明提供一种路由结构和显示面板。 路由结构包括多个路由，分开设置。 每个路由对应于符号，并且该符号被布置在路由上以充当路由的一部分以进行电力。 以这种方式，本发明的路由结构和显示面板允许扩展路由宽度，有效降低RC常数和能量消耗，并提高成品率。

公开(公告)号：US20100101140A1

公开(公告)日：2010-04-29

申请号：US12258560

申请日：2008-10-27

申请人： John E. Hoots ,  Phillip E. Bureman ,  Hua Zheng

发明人： John E. Hoots ,  Phillip E. Bureman ,  Hua Zheng

IPC分类号： C10L1/18

CPC分类号： C10L1/1822 ,  C10L1/00 ,  C10L1/06 ,  C10L1/14 ,  C10L1/1608 ,  C10L1/1616 ,  C10L1/182 ,  C10L1/1881 ,  C10L1/1883 ,  C10L1/2222 ,  C10L10/04

摘要： Disclosed is a method of monitoring and optimizing the concentration of a denaturant composition in a fuel ethanol. The method includes adding a known amount of the denaturant composition to the fuel ethanol to create a treated fuel ethanol. A measured spectroscopic absorbance or transmittance signal provides information for determining the concentration of the denaturant composition in the fuel ethanol. A component in the denaturant composition is capable of providing the spectroscopic absorbance or transmittance signal or capable of being chemically derivatized to provide a spectroscopic absorbance or transmittance signal. Based upon the measured spectroscopic absorbance or transmittance signal, the concentration of the additive composition in the fuel ethanol may be adjusted.

摘要翻译： 公开了一种监测和优化燃料乙醇中变性剂组合物浓度的方法。 该方法包括向燃料乙醇中加入已知量的变性剂组合物以产生经处理的燃料乙醇。 测量的光谱吸收或透射信号提供用于确定燃料乙醇中变性剂组合物浓度的信息。 变性剂组合物中的组分能够提供光谱吸收或透射信号或能够被化学衍生化以提供光谱吸收或透射信号。 基于测量的光谱吸收或透射信号，可以调节燃料乙醇中的添加剂组合物的浓度。

公开(公告)号：US20050270058A1

公开(公告)日：2005-12-08

申请号：US11200372

申请日：2005-08-09

申请人： Joseph Sher ,  David Siek ,  Huy Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

发明人： Joseph Sher ,  David Siek ,  Huy Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

IPC分类号： G01R31/26 ,  G01R31/30 ,  G11C5/14 ,  G11C29/02 ,  G11C29/12

CPC分类号： G11C29/02 ,  G01R31/3004 ,  G11C5/145 ,  G11C5/146 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C2029/5004

摘要： A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.

摘要翻译： 用于产生用于封装的集成电路存储器件的内部电压的电压产生电路是可控的，以提供用于存储器件测试的电压的增量调节。 电压产生电路允许通过常规测试功能在执行标准中通过施加测试信号来外部控制存储器件的内部产生的电压，例如衬底电压Vbb，DVC 2电压和泵浦电压Vccp。 诸如静态刷新测试，逻辑1s和0s边缘测试等设备测试等，用于封装的存储器件。 此外，提供了包括可编程逻辑器件（例如抗熔丝）的可编程电路，其可编程以将电压维持在其调节幅度。