Configurable data integrity mode, and memory device including same

    公开(公告)号:US10891184B2

    公开(公告)日:2021-01-12

    申请号:US16419430

    申请日:2019-05-22

    Abstract: An integrated circuit device can comprise addressable memory, and a receiver. Data integrity logic can be coupled to the input data path and configured to receive a data stream having a reference address, and a plurality of data chunks with data integrity codes. Also, the data integrity logic can include a configuration store to store configuration data for the data integrity checking. Also, the integrated circuit can include logic to parse the data chunks and the data integrity codes from the data stream, and logic to compute computed data integrity codes of data chunks in the received data stream, and compare the computed data integrity codes with received data integrity codes to test for data errors in the received data stream. The data integrity logic includes logic responsive to the configuration data that control the data integrity logic. In one aspect, the data integrity data indicates a floating boundary data integrity mode or a fixed boundary data integrity mode.

    Non-volatile memory with physical unclonable function and random number generator

    公开(公告)号:US10855477B2

    公开(公告)日:2020-12-01

    申请号:US15857341

    申请日:2017-12-28

    Abstract: A device which can be implemented on a single packaged integrated circuit or a multichip includes a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce an initial key and to store the initial key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The device can include logic to use a random number generator to generate a random number, and logic to combine the initial key and the random number to produce an enhanced key. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce the initial key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set.

    Nested wrap-around memory access with fixed offset

    公开(公告)号:US10162751B2

    公开(公告)日:2018-12-25

    申请号:US15139252

    申请日:2016-04-26

    Abstract: A nested wrap-around technology includes an address counter and associated logic for generating addresses to perform a nested wrap-around access operation. The nested wrap-around access operation may be a read or a write operation. A wrap-around section length and a wrap-around count define a wrap-around block. A wrap starting address, initially set to a supplied start address, is offset from a lower boundary of a wrap-around section. Access starts at a wrap starting address and proceeds in a wrap-around manner within a wrap-around section. After access of the address immediately preceding the wrap starting address, the wrap starting address is incremented by the wrap-around section length, or, if the wrap-around section is the last one in the wrap-around block, the wrap starting address is set to the lower boundary of the wrap-around block plus the offset. Access continues until a termination event.

    Power source for memory circuitry
    77.
    发明授权

    公开(公告)号:US09881654B2

    公开(公告)日:2018-01-30

    申请号:US14877723

    申请日:2015-10-07

    CPC classification number: G11C5/145

    Abstract: An integrated circuit comprises a power supply input pin receiving an off-chip supply voltage having a variable current, an on-chip power source powered by the off-chip supply voltage and providing a regulated current, a memory array, and a set of one or more circuits coupled to the memory array and powered by the regulated current from the on-chip power source. The IC can include control circuitry performing memory operations on the memory array, said control circuitry powered by at least the off-chip supply voltage from the power supply pin.

    Power source for memory circuitry
    80.
    发明授权
    Power source for memory circuitry 有权
    存储器电路的电源

    公开(公告)号:US09536575B2

    公开(公告)日:2017-01-03

    申请号:US14877692

    申请日:2015-10-07

    CPC classification number: G11C5/145 G11C7/12 G11C8/08

    Abstract: An integrated circuit comprises a power supply input pin for receiving an off-chip supply voltage which can have a variable current, an on-chip power source to be powered by the off-chip supply voltage and which can provide a regulated current, a set of one or more circuits to be powered by at least one of the off-chip supply voltage and the on-chip power source, a configuration memory storing a set of one or more memory settings that indicate whether a circuit of said set of one or more circuits is powered by the on-chip power source, and control circuitry responsive to the at least one memory setting to control whether said circuit of said set of one or more circuits is powered by the on-chip power source.

    Abstract translation: 集成电路包括用于接收可以具有可变电流的芯片外电源电压的电源输入引脚,由芯片外电源电压供电并且可以提供调节电流的片上电源,一组 一个或多个电路由芯片外电源电压和片上电源中的至少一个供电;配置存储器,存储一组或多个存储器设置,其指示所述一组或多个电路 更多的电路由片上电源供电,以及响应于至少一个存储器设置的控制电路,以控制所述一组或多个电路的所述电路是否由片上电源供电。

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