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86 条记录 (耗时 0.044 秒)

    Back-end renaming in a continual flow processor pipeline
    71.
    发明授权
    Back-end renaming in a continual flow processor pipeline 有权
    在持续流处理器管道中进行后端重命名

    公开(公告)号：US07487337B2

    公开(公告)日：2009-02-03

    申请号：US10953761

    申请日：2004-09-30

    申请人： Haitham Akkary ,  Ravi Rajwar ,  Srikanth T. Srinivasan

    发明人： Haitham Akkary ,  Ravi Rajwar ,  Srikanth T. Srinivasan

    IPC分类号： G06F9/30 ,  G06F15/00

    CPC分类号： G06F9/3842 ,  G06F9/384

    摘要： Embodiments of the present invention relate to a system and method for comparatively increasing processor throughput and relieving pressure on the processor's scheduler and register file by diverting instructions dependent on long-latency operations from a flow of the processor pipeline and re-introducing the instructions into the flow when the long-latency operations are completed. In this way, the instructions do not tie up resources and overall instruction throughput in the pipeline is comparatively increased. Before the instructions are diverted from the pipeline, they may undergo a conventional process to map logical registers of the instructions to physical registers. Before the instructions are re-introduced into the pipeline, the physical registers mapped according to the conventional process may be re-mapped to other physical registers, thereby efficiently preserving correct program sequence information.

    摘要翻译： 本发明的实施例涉及一种用于相对增加处理器吞吐量并减轻处理器调度器和寄存器文件上的压力的系统和方法，该方法通过根据来自处理器流水线的长度等待时间操作转移指令，并将指令重新引入到 长时间延迟操作完成时流量。 以这种方式，指令不会占用资源，并且管道中的总体指令吞吐量相对增加。 在指令从流水线转移之前，它们可以经历常规过程，将指令的逻辑寄存器映射到物理寄存器。 在将指令重新引入到流水线之前，根据常规过程映射的物理寄存器可以重新映射到其他物理寄存器，从而有效地保留正确的程序序列信息。

    Concurrent Execution of Critical Sections by Eliding Ownership of Locks
    72.
    发明申请
    Concurrent Execution of Critical Sections by Eliding Ownership of Locks 有权
    通过确定锁定所有权并行执行关键部分

    公开(公告)号：US20070186215A1

    公开(公告)日：2007-08-09

    申请号：US11539731

    申请日：2006-10-09

    申请人： Ravi Rajwar ,  James Goodman

    发明人： Ravi Rajwar ,  James Goodman

    IPC分类号： G06F9/46

    CPC分类号： G06F9/528 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/52 ,  G06F12/0808 ,  G06F12/0844 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/128 ,  G06F12/1458 ,  G06F12/1475 ,  G06F2212/1041 ,  G06F2212/1052 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/69

    摘要： One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.

    摘要翻译： 本发明的一个实施例提供一种通过推测性地执行代码的关键部分来有助于避免锁定的系统。 在操作期间，系统允许进程在程序中推测性地执行代码的关键部分而不首先获得与关键部分相关联的锁定。 如果该过程随后完成关键部分而没有遇到来自另一进程的干扰数据访问，则系统进行在推测执行期间所做的更改，并且通过关键部分恢复程序的正常非推测性执行。 否则，如果在执行关键部分期间遇到来自其他进程的干扰数据访问，则系统将丢弃在推测执行期间所做的更改，并尝试重新执行临界部分。

    Method and apparatus for instruction latency tolerant execution in an out-of-order pipeline
    74.
    发明申请
    Method and apparatus for instruction latency tolerant execution in an out-of-order pipeline 审中-公开
    用于在无序流水线中执行指令等待时间的方法和装置

    公开(公告)号：US20060277398A1

    公开(公告)日：2006-12-07

    申请号：US11145409

    申请日：2005-06-03

    申请人： Haitham Akkary ,  Ravi Rajwar ,  Srikanth Srinivasan ,  Christopher Wilkerson

    发明人： Haitham Akkary ,  Ravi Rajwar ,  Srikanth Srinivasan ,  Christopher Wilkerson

    IPC分类号： G06F9/44

    CPC分类号： G06F9/3836 ,  G06F9/3814 ,  G06F9/383 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

    摘要： A method and apparatus for setting aside a long-latency micro-operation from a reorder buffer is disclosed. In one embodiment, a long-latency micro-operation would conventionally stall a reorder buffer. Therefore a secondary buffer may be used to temporarily store that long-latency micro-operation, and other micro-operations depending from it, until that long-latency micro-operation is ready to execute. These micro-operations may then be reintroduced into the reorder buffer for execution. The use of poisoned bits may be used to ensure correct retirement of register values merged from both pre- and post-execution of the micro-operations which were set aside in the secondary buffer.

    摘要翻译： 公开了一种用于从重排序缓冲器中排除长延迟微操作的方法和装置。 在一个实施例中，长时间延迟微操作通常会阻止重新排序缓冲器。 因此，可以使用辅助缓冲器来临时存储长延迟微操作以及依赖于其的微操作，直到长时间延迟微操作准备好执行。 然后可以将这些微操作重新引入重排序缓冲器中以供执行。 可以使用中毒的位来确保正确地退出从辅助缓冲器中放置的微操作执行之前和之后合并的寄存器值。

    Method of using delays to speed processing of inferred critical program portions
    75.
    发明授权
    Method of using delays to speed processing of inferred critical program portions 有权
    使用延迟加速推断的关键程序部分的方法

    公开(公告)号：US06460124B1

    公开(公告)日：2002-10-01

    申请号：US09693030

    申请日：2000-10-20

    申请人： Alain Kagi ,  James R. Goodman ,  Ravi Rajwar

    发明人： Alain Kagi ,  James R. Goodman ,  Ravi Rajwar

    IPC分类号： G06F1208

    CPC分类号： G06F12/0806 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/528

    摘要： Critical sections of a program, providing exclusive access to shared data in a multi-processor architecture may be inferred from standard instructions and used to invoke a cache protocol that delays the response of requests of other cache and thus counter intuitively improving performance of the system. During this delay, read-only copies of data may be provided and the delay may recognize two priorities of requests, one of which is not delayed so as to improve the release of locks held by different processors.

    摘要翻译： 可以从标准指令推断程序的关键部分，提供对多处理器架构中的共享数据的独占访问，并且用于调用延迟其他缓存的请求的响应的缓存协议，从而直观地改善系统的性能。 在该延迟期间，可以提供数据的只读副本，并且延迟可以识别请求的两个优先级，其中一个优先级不被延迟，以便改善由不同处理器保持的锁的释放。

    Vector compare-and-exchange operation
    79.
    发明授权
    Vector compare-and-exchange operation 有权
    向量比较和交换操作

    公开(公告)号：US08996845B2

    公开(公告)日：2015-03-31

    申请号：US12644529

    申请日：2009-12-22

    申请人： Ravi Rajwar ,  Andrew T. Forsyth

    发明人： Ravi Rajwar ,  Andrew T. Forsyth

    IPC分类号： G06F15/00 ,  G06F15/76 ,  G06F9/30

    CPC分类号： G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30087

    摘要： A vector compare-and-exchange operation is performed by: decoding by a decoder in a processing device, a single instruction specifying a vector compare-and-exchange operation for a plurality of data elements between a first storage location, a second storage location, and a third storage location; issuing the single instruction for execution by an execution unit in the processing device; and responsive to the execution of the single instruction, comparing data elements from the first storage location to corresponding data elements in the second storage location; and responsive to determining a match exists, replacing the data elements from the first storage location with corresponding data elements from the third storage location.

    摘要翻译： 通过以下操作来执行向量比较和交换操作：通过处理设备中的解码器进行解码，指定在第一存储位置，第二存储位置和第二存储位置之间的多个数据元素的向量比较和交换操作的单个指令， 和第三存储位置; 发出由处理装置中的执行单元执行的单个指令; 并且响应于所述单个指令的执行，将来自所述第一存储位置的数据元素与所述第二存储位置中的相应数据元素进行比较; 并且响应于确定匹配存在，用来自第三存储位置的相应数据元素从第一存储位置替换数据元素。