公开(公告)号：US20050180242A1

公开(公告)日：2005-08-18

申请号：US11103551

申请日：2005-04-12

申请人： Hiroyoshi Tomita ,  Toshiya Uchida

发明人： Hiroyoshi Tomita ,  Toshiya Uchida

IPC分类号： G11C7/12 ,  G11C11/406 ,  G11C11/4094 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C11/406 ,  G11C11/4094 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2211/4065

摘要： A semiconductor storage device has a memory cell (501, 502) storing data; bit lines (BL1, BL2) connected to the memory cell, allowing therethrough data input or output to or from the memory cell; a sense amplifier (506a) connected to said bit lines, amplifying data on the bit lines; and a switching transistor (505a) connecting or disconnecting the bit line connected to the memory cell to or from the bit line connected to the sense amplifier. The switching transistor operates differently in a first memory cell access operation and in a second memory cell access operation.

摘要翻译： 半导体存储装置具有存储数据的存储单元（501,502） 连接到存储单元的位线（BL 1，BL 2），允许数据输入或输出到存储单元; 连接到所述位线的读出放大器（506a），放大位线上的数据; 以及开关晶体管（505a），连接或断开与连接到读出放大器的位线连接到存储单元的位线。 开关晶体管在第一存储器单元存取操作和第二存储单元存取操作中的操作方式不同。

公开(公告)号：US06813696B2

公开(公告)日：2004-11-02

申请号：US10694982

申请日：2003-10-29

申请人： Tatsuya Kanda ,  Hiroyoshi Tomita

发明人： Tatsuya Kanda ,  Hiroyoshi Tomita

IPC分类号： G06F1200

CPC分类号： G11C7/1087 ,  G11C7/1021 ,  G11C7/1039 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/222 ,  G11C29/14

摘要： The present invention relates to a SDRAM and its control method which write or read data in synchronization with the external clock and its object is to provide a semiconductor memory device and its method which can be easily tested and evaluated by the conventional memory test equipment having a transfer type which transfers the data in synchronization with the rising and falling edges of the external clock. The semiconductor memory device has a write amplifier control section 14 and I/O data buffer/register 22 as a data transfer circuit corresponding to the data transfer type for the DDR type and SDR type. Also, a mode register 28 is formed to be used as a switch signal to switch the data transfer circuit to either DDR type or SDR type.

摘要翻译： 本发明涉及一种与外部时钟同步写入或读取数据的SDRAM及其控制方法，其目的在于提供一种半导体存储器件及其方法，该半导体存储器件及其方法可以容易地由具有 传输类型与外部时钟的上升沿和下降沿同步传输数据。 半导体存储器件具有写入放大器控制部分14和I / O数据缓冲器/寄存器22，作为对应于DDR类型和SDR类型的数据传输类型的数据传输电路。 此外，模式寄存器28形成为用作切换信号以将数据传输电路切换为DDR类型或SDR类型。

公开(公告)号：US06339353B1

公开(公告)日：2002-01-15

申请号：US09542454

申请日：2000-04-04

申请人： Hiroyoshi Tomita ,  Naoharu Shinozaki

发明人： Hiroyoshi Tomita ,  Naoharu Shinozaki

IPC分类号： H03K3356

CPC分类号： G11C7/109 ,  G11C8/06 ,  H03K3/012 ,  H03K3/356121 ,  H03K3/356139 ,  H03K5/133 ,  H03K5/1534

摘要： The present invention provides an input circuit having small current consumption in a clock synchronization type semiconductor integrated circuit. The input circuit is activated by an activation signal to receive an input signal and an activation signal generating circuit generates the activation signal. The activation signal generating circuit activates intermittently the activation signal for a time shorter than a period of a clock signal and including a setup time and a hold time of the input signal in order to activate the input circuit. The input circuit is activated only for the limited time of one period of the clock signal and therefore current consumption can be reduced.

摘要翻译： 本发明提供一种在时钟同步型半导体集成电路中具有小电流消耗的输入电路。 输入电路由激活信号激活以接收输入信号，激活信号产生电路产生激活信号。 激活信号发生电路间歇地激活比时钟信号周期短的时间的激活信号，并且包括输入信号的建立时间和保持时间，以激活输入电路。 输入电路仅在时钟信号的一个周期的有限时间内被激活，因此可以减少电流消耗。

公开(公告)号：US06317372B1

公开(公告)日：2001-11-13

申请号：US09528983

申请日：2000-03-20

申请人： Tomonori Hayashi ,  Naoharu Shinozaki ,  Hiroyoshi Tomita

发明人： Tomonori Hayashi ,  Naoharu Shinozaki ,  Hiroyoshi Tomita

IPC分类号： G11C2900

CPC分类号： G11C29/40 ,  G11C29/34 ,  G11C29/48

摘要： An input conversion unit converts serial data supplied from the exterior into parallel data. Each of the converted parallel data is respectively written into a plurality of memory cell areas. An output conversion unit converts parallel data constructed by data read from each memory cell area into serial data. An operational unit is activated during a testing mode so as to logically operate on the parallel data read from each memory cell area. By writing predetermined data into each memory cell area in advance, it is confirmed by a logic operation that correct data is stored in each memory cell area. The data can be checked simultaneously for the plurality of memory cell areas so that the operation test in the memory cell areas can be carried out at high speed. Besides, serial data accepted, twice per cycle of a data strobe signal, is converted into parallel data. Each of the converted parallel data is respectively written into a first memory cell area and a second memory cell area. Parallel data read from the first and second memory cell area is logically operated in a testing mode and the operation result is output at once in synchronization with the clock signal. Accordingly, the data can be checked simultaneously for the first and the second memory cell area so that the operation test in the memory cell areas can be carried out at high speed.

摘要翻译： 输入转换单元将从外部提供的串行数据转换为并行数据。 每个转换的并行数据分别写入多个存储单元区域。 输出转换单元将从每个存储单元区域读取的数据构成的并行数据转换为串行数据。 在测试模式期间激活操作单元，以便对从每个存储单元区域读取的并行数据进行逻辑运算。 通过预先将预定数据写入每个存储单元区域，通过逻辑运算来确认正确的数据被存储在每个存储单元区域中。 可以同时检查多个存储单元区域的数据，使得可以高速地执行存储单元区域中的操作测试。 此外，接受数据选通信号每周期两次的串行数据被转换为并行数据。 每个转换的并行数据分别被写入第一存储器单元区域和第二存储器单元区域中。 从第一和第二存储单元区域读取的并行数据在测试模式下逻辑运行，并且与时钟信号同步地一次输出运算结果。 因此，可以同时检查第一和第二存储单元区域的数据，使得可以高速地执行存储单元区域中的操作测试。

公开(公告)号：US06239631B1

公开(公告)日：2001-05-29

申请号：US09377104

申请日：1999-08-19

申请人： Shinya Fujioka ,  Hiroyoshi Tomita

发明人： Shinya Fujioka ,  Hiroyoshi Tomita

IPC分类号： H03L700

CPC分类号： G11C7/1093 ,  G06F5/06 ,  G11C7/1087 ,  G11C7/222 ,  H03L7/00

摘要： One aspect of the present invention is characterized in that an input buffer circuit constitutes either 2 sets, or a plurality of sets relative to 1 input signal, either a pair of complementary internal clocks, or a plurality of internal clocks are generated by frequency-dividing a supplied clock inside the integrated circuit device, and input signals are received and latched either in synchronization with a pair of complementary clocks, or in synchronization with a plurality of clocks in accordance with an input buffer of either 2 sets or a plurality of sets. The output of input buffers of either 2 sets or a plurality of sets are combined by a combining circuit, and supplied internally. An H level or an L level period is set for the internally-generated internal clock so that outputs from the various input buffers are not in contention with one another. According to the present invention, the operation of input buffers of a plurality of sets are synchronized with internal clocks of a slower speed than a supplied clock, thus enabling the reliable receive of input signals.

摘要翻译： 本发明的一个方面的特征在于，输入缓冲电路构成2组或相对于1个输入信号的多组，一对互补的内部时钟或多个内部时钟通过分频产生 集成电路器件内的提供的时钟和输入信号可以与一对互补时钟同步地接收和锁存，或者根据两组或多组的输入缓冲器与多个时钟同步地被接收和锁存。 2组或多组的输入缓冲器的输出由组合电路组合，并在内部提供。 为内部产生的内部时钟设置一个H电平或一个L电平周期，使得各种输入缓冲器的输出不会相互竞争。 根据本发明，多个组的输入缓冲器的操作与比所提供的时钟慢的内部时钟同步，因此能够可靠地接收输入信号。

公开(公告)号：US06181184B2

公开(公告)日：2001-01-30

申请号：US09089397

申请日：1998-06-03

申请人： Masafumi Yamazaki ,  Hiroyoshi Tomita

发明人： Masafumi Yamazaki ,  Hiroyoshi Tomita

IPC分类号： H03H1126

CPC分类号： H03K5/133 ,  H03K5/131 ,  H03K2005/00058 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087

摘要： A variable delay circuit includes a load on a signal transfer line, at least one transistor connected to the signal transfer line. Each transistor is controlled by a gate voltage thereof so that a signal on the signal transfer line is delayed in response to a magnitude of the gate capacitance connected thereto.

摘要翻译： 可变延迟电路包括信号传输线上的负载，连接到信号传输线的至少一个晶体管。 每个晶体管由其栅极电压控制，使得信号传输线上的信号响应于与其连接的栅极电容的大小而被延迟。

公开(公告)号：US6144595A

公开(公告)日：2000-11-07

申请号：US131880

申请日：1998-08-10

申请人： Osamu Hirooka ,  Hiroyoshi Tomita ,  Tatsuya Kanda

发明人： Osamu Hirooka ,  Hiroyoshi Tomita ,  Tatsuya Kanda

IPC分类号： G01R31/28 ,  G11C11/401 ,  G11C11/407 ,  G11C29/02 ,  G11C29/12 ,  G11C29/34 ,  G11C7/00

CPC分类号： G11C29/12 ,  G11C29/02

摘要： A semiconductor device outputs data from a plurality of data nodes during a normal-operation mode, and outputs a test result from at least one of the data nodes during a test-operation mode. The semiconductor device includes a plurality of data-bus lines which convey the data with respect to the data nodes, and a data-bus switch which allows only the data-bus lines corresponding to the at least one of the data nodes to be driven in a first condition of the test-operation mode, and which allows all of the data-bus lines corresponding to the data nodes to be driven in a second condition of the test-operation mode.

摘要翻译： 半导体器件在正常操作模式期间从多个数据节点输出数据，并且在测试操作模式期间从至少一个数据节点输出测试结果。 半导体器件包括相对于数据节点传送数据的多条数据总线，以及数据总线开关，该数据总线开关只允许与至少一个数据节点相对应的数据总线线驱动 测试操作模式的第一条件，并且允许在测试操作模式的第二条件下驱动对应于数据节点的所有数据总线。

公开(公告)号：US5939913A

公开(公告)日：1999-08-17

申请号：US19197

申请日：1998-02-05

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G11C11/417 ,  G06F1/10 ,  G11C7/00 ,  G11C7/22 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/13 ,  H03K5/135 ,  H03L7/00 ,  H03L7/081 ,  H03L7/06

CPC分类号： H03L7/0805 ,  G11C7/22 ,  H03K5/131 ,  H03K5/135 ,  H03L7/0814 ,  Y10S331/02

摘要： The present invention supplies a first delay control signal generated by a DLL circuit to a first variable delay circuit which generates a control clock by delaying a clock for a prescribed time period. The DLL circuit comprises: a first delay loop, comprising a second variable delay circuit and a third variable delay circuit connected in series, to which the clock is supplied; a phase comparator which is supplied with a clock which delays an integral factor of 360.degree. of said clock from the clock, as a reference clock, and the output of the first delay loop, as a variable clock; and a delay control circuit which generates said first delay control signal in accordance with a phase comparison result signal from the phase comparator such that there is no phase difference with said two supplied clocks. The second variable delay circuit is supplied with the first delay control signal. The third variable delay circuit has a delay time of .beta..degree. in accordance with a second delay control signal generated by a .beta..degree. detecting circuit. As a result, the second variable delay circuit generates a delay time of approximately 360.degree.-.beta..degree.=.alpha..degree.. By similarly controlling the delay time of the first variable delay circuit by means of this first delay control signal, the control clock output therefrom is phase delayed by .alpha..degree. from the clock.

摘要翻译： 本发明将由DLL电路产生的第一延迟控制信号提供给第一可变延迟电路，该第一可变延迟电路通过将时钟延迟规定的时间周期来产生控制时钟。 DLL电路包括：第一延迟环路，包括串联连接的第二可变延迟电路和第三可变延迟电路，时钟被提供给该延迟电路; 相位比较器，其被提供有时钟，该时钟将来自时钟的时钟的360°的积分因子作为参考时钟和第一延迟环的输出作为可变时钟; 以及延迟控制电路，其根据来自相位比较器的相位比较结果信号产生所述第一延迟控制信号，使得与所述两个提供的时钟没有相位差。 第二可变延迟电路被提供有第一延迟控制信号。 第三可变延迟电路根据由βDEG检测电路产生的第二延迟控制信号具有βDEG的延迟时间。 结果，第二可变延迟电路产生大约360°-β°=α°的延迟时间。 通过类似地通过该第一延迟控制信号控制第一可变延迟电路的延迟时间，其输出的控制时钟从时钟相位延迟α°。

公开(公告)号：US5901101A

公开(公告)日：1999-05-04

申请号：US919505

申请日：1997-08-28

申请人： Takaaki Suzuki ,  Masao Nakano ,  Hiroyoshi Tomita ,  Yasuharu Sato ,  Kotoku Sato ,  Nobutaka Taniguchi

发明人： Takaaki Suzuki ,  Masao Nakano ,  Hiroyoshi Tomita ,  Yasuharu Sato ,  Kotoku Sato ,  Nobutaka Taniguchi

IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C11/406

摘要： In a semiconductor memory device operable in synchronism with a clock signal externally supplied thereto, there are provided a first part which detects a state of a predetermined signal after a given command is input to the semiconductor memory; and a second part which sets, on the basis of the state of the predetermined signal, the semiconductor memory device to a self-refresh mode in which a refresh operation is carried out without an external signal.

摘要翻译： 在与外部提供给其的时钟信号同步操作的半导体存储器件中，提供了第一部分，其在将给定命令输入到半导体存储器之后检测预定信号的状态; 以及第二部分，其基于预定信号的状态将半导体存储器件设置为在没有外部信号的情况下执行刷新操作的自刷新模式。

公开(公告)号：US5384726A

公开(公告)日：1995-01-24

申请号：US193535

申请日：1994-02-08

申请人： Hiroyoshi Tomita ,  Makoto Yanagisawa ,  Yukinori Kodama

发明人： Hiroyoshi Tomita ,  Makoto Yanagisawa ,  Yukinori Kodama

IPC分类号： G11C7/06 ,  G11C5/06

CPC分类号： G11C7/065

摘要： A semiconductor memory device includes a memory cell array in which a number of sense amplifiers are provided, a plurality of segmented drive lines each connected to a group of sense amplifiers for driving the same, each of the segmented drive lines being formed of first and second drive line segments forming a pair, and a number of trunks for supplying electric power to the segmented drive lines. Each of the trunks includes a first conductor strip extending from a first side of the memory cell array toward a second side for connection to a plurality of the first drive line segments upon crossing the same, and a second conductor strip extending from the second side of the memory cell array toward the first side for connection to a plurality of the second drive line segments upon crossing the same. The first and second conductor strips have distal end parts having a reduced width and a mutually complementary shape, such that the first and second conductor strips are disposed to form a straight strip having a substantially constant width throughout the memory cell array.

摘要翻译： 一种半导体存储器件包括其中提供多个读出放大器的存储单元阵列，多个分段驱动线，每个驱动线连接到用于驱动读出放大器的一组读出放大器，每个分段驱动线由第一和第二 形成一对的驱动线段和用于向分段驱动线提供电力的多个中继线。 每个中继线包括从存储单元阵列的第一侧向第二侧延伸的第一导体条，用于在与第一驱动线段交叉时与多个第一驱动线段连接，第二导体条从第二侧延伸 所述存储单元阵列朝向所述第一侧，用于在与所述第二驱动线段交叉时连接到所述第二驱动线段。 第一和第二导体条具有具有减小的宽度和相互互补形状的远端部分，使得第一和第二导体条被设置成形成整个存储单元阵列具有基本恒定的宽度的直条。